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MCIMX287CVM4B Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MCIMX287CVM4B Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 70 page  i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1 10 Freescale Semiconductor 2.1 Special Signal Considerations Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4, “Package Information and Contact Assignments.” Signal descriptions are provided in the reference manual. SSP(4) Synchronous serial port Connectivity peripherals The synchronous serial port is a flexible interface for inter-IC and removable media control and communication. The SSP supports master operation of SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit and 4-bit MS modes. The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP also supports slave operation for the SPI and SSI modes. The SSP has a dedicated DMA channel in the bridge and can also be controlled directly by the CPU through PIO registers. Each of the four SSP modules is independent of the other and can have separate SSPCLK frequencies. TIMROT Timers and Rotary Decoder Timer peripherals This module implements four timers and a rotary decoder. The timers and decoder can take their inputs from any of the pins defined for PWM, rotary encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM pins can be inputs or outputs, depending on the application. USBOTG USBHOST High-speed USB on-the-go Connectivity peripherals The USB module provides high-performance USB On-The-Go (OTG) and host functionality (up to 480 Mbps), compliant with the USB 2.0 specification and the OTG supplement. The module has DMA capabilities for handling data transfer between internal buffers and system memory. When the OTG controller works in device mode, it can only work in FS or HS mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another for the host port.) USBPHY Integrated USB PHY Connectivity peripherals The integrated USB 2.0 PHY macrocells are capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed (FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps. The integrated PHYs provide a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB connector. Table 5. Signal Considerations Signal Descriptions PSWITCH The pin is used for chip power on or recovery. VDDIO can be applied to PSWITCH through a 10 k Ω resistor. This is necessary in order to enter the chip’s firmware recovery. The on-chip circuitry prevents the actual voltage on the pin from exceeding acceptable levels. VDDXTAL This pin is an output of i.MX28. Should be coupled to ground with a 0.1 uF capacitor. User should not supply external power to this pin. BATTERY This pin should be connected to the battery with minimal resistance. It provides charging current to the battery. See the “Power Supply” section of the reference manual for details. Table 4. i.MX28 Digital and Analog Modules (continued) Block Mnemonic Block Name Subsystem Brief Description |
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