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ICE2AS01G Datasheet(PDF) 10 Page - Infineon Technologies AG |
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ICE2AS01G Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 24 page  Datasheet 10 30 Jun 2006 Preliminary Data ICE2AS01/S01G ICE2BS01/S01G Functional Description Figure 11 Start Up Phase 3.4 Oscillator and Frequency Reduction 3.4.1 Oscillator The oscillator generates a frequency fswitch = 100kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a max. duty cycle limitation of Dmax=0.72. 3.4.2 Frequency Reduction The frequency of the oscillator is depending on the voltage at pin FB. The dependence is shown in Figure 12. This feature allows a power supply to operate at lower frequency at light loads thus lowering the switching losses while maintaining good cross regulation performance and low output ripple. In case of low power the power consumption of the whole SMPS can now be reduced very effective. The minimal reachable frequency is limited to 20kHz / 21.5 kHz to avoid audible noise in any case. Figure 12 Frequency Dependence 3.5 Current Limiting There is a cycle by cycle current limiting realised by the Current-Limit Comparator to provide an overcurrent detection. The source current of the external Power Switch is sensed via an external sense resistor RSense. By means of RSense the source current is transformed to a sense voltage VSense. When the voltage VSense exceeds the internal threshold voltage Vcsth the Current-Limit-Comparator immediately turns off the gate drive. To prevent the Current Limiting from distortions caused by leading edge spikes a Leading Edge Blanking is integrated at the Current Sense. Furthermore a Propagation Delay Compensation is added to support the immediate shut down of the Power Switch in case of overcurrent. 3.5.1 Leading Edge Blanking Figure 13 Leading Edge Blanking Each time when the external Power Switch is switched on a leading spike is generated due to the primary-side capacitances and secondary-side rectifier reverse t t V SoftS t 5.3V 4.8V T Soft-Start V OUT V FB V OUT T Start-Up f standby f norm 1,0 1,1 1,2 1,3 1,4 1,5 1,6 1,7 1,8 1,9 2 FB V V kHz f norm: ICE2BS01(G) ICE2AS01(G) 67kHz 100kHz f standby: 20kHz 21.5kHz t V Sense V csth t LEB = 220ns |
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