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LTC2259-14 Datasheet(PDF) 7 Page - Linear Technology |
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LTC2259-14 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 36 page  7 21454312p LTC2145-12/ LTC2144-12/LTC2143-12 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTC2145-12 LTC2144-12 LTC2143-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input Sine Wave Input l 101.5 102.2 TBD 79.8 80.3 TBD 60.4 60.9 TBD mA mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 7.3 6.2 4.7 mA PDISS Power Dissipation DC Input Sine Wave Input, OVDD = 1.2V l 183 193 TBD 144 152 TBD 109 115 TBD mW mW LVDS Output Mode VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 103.4 104.6 TBD 81.6 82.8 TBD 62.1 63.4 TBD mA mA IOVDD Digital Supply Current (0VDD = 1.8V) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 30.6 57.9 TBD 30.3 57.6 TBD 30.1 57.3 TBD mA mA PDISS Power Dissipation Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 241 293 TBD 201 253 TBD 166 217 TBD mW mW All Output Modes PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 16 16 16 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No increase for Nap or Sleep Modes) 20 20 20 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTC2145-12 LTC2144-12 LTC2143-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Note 10) l 1 125 1 105 1 80 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 500 500 4.52 2 4.76 4.76 500 500 5.93 2 6.25 6.25 500 500 ns ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 3.8 2 4 4 500 500 4.52 2 4.76 4.76 500 500 5.93 2 6.25 6.25 500 500 ns ns tAP Sample-and-Hold Acquisition Delay Time 000 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode Double Data Rate Mode 6 6.5 Cycles Cycles |
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Similar Description - LTC2259-14 |
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