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LTC2262-14 Datasheet(PDF) 7 Page - Linear Technology |
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LTC2262-14 Datasheet(HTML) 7 Page - Linear Technology |
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7 / 36 page  7 21421012p LTC2142-12/ LTC2141-12/LTC2140-12 POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS LTC2142-12 LTC2141-12 LTC2140-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX CMOS Output Modes: Full Data Rate and Double Data Rate VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.8 1.9 1.1 1.8 1.9 1.1 1.8 1.9 V IVDD Analog Supply Current DC Input Sine Wave Input l 50.9 51.3 TBD 35.9 36.2 TBD 26.9 27 TBD mA mA IOVDD Digital Supply Current Sine Wave Input, OVDD = 1.2V 3.8 2.4 1.5 mA PDISS Power Dissipation DC Input Sine Wave Input, OVDD = 1.2V l 91.6 96.9 TBD 64.6 68 TBD 48.4 50.4 TBD mW mW LVDS Output Mode VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V IVDD Analog Supply Current Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 52.6 53.8 TBD 37.4 38.7 TBD 28.3 29.5 TBD mA mA IOVDD Digital Supply Current (0VDD = 1.8V) Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 30 57.4 TBD 29.6 57.1 TBD 29.3 56.8 TBD mA mA PDISS Power Dissipation Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode l 149 200 TBD 121 172 TBD 104 155 TBD mW mW All Output Modes PSLEEP Sleep Mode Power 1 1 1 mW PNAP Nap Mode Power 10 10 10 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled (No Increase for Nap or Sleep Modes) 20 20 20 mW TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS LTC2142-12 LTC2141-12 LTC2140-12 UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX fS Sampling Frequency (Note 10) l 1 65 1 40 1 25 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 2 7.69 7.69 500 500 11.88 2 12.5 12.5 500 500 19 2 20 20 500 500 ns ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off Duty Cycle Stabilizer On l l 7.3 2 7.69 7.69 500 500 11.88 2 12.5 12.5 500 500 19 2 20 20 500 500 ns ns tAP Sample-and-Hold Acquisition Delay Time 000 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate) tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode Double Data Rate Mode 6 6.5 Cycles Cycles |
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