Smallest TEC Power Drivers for Optical

Modules

2

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ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

SHDN, MAXV, MAXIP, MAXIN,

CTLI to GND .........................................................-0.3V to +6V

COMP, FREQ, OS1, OS2, CS, REF,

PGND1, PGND2 to GND .......................................-0.3V to +0.3V

COMP, REF, ITEC short to GND....................................Indefinite

LX Current (Note 1) ........................................±2.25A LX Current

6 x 6 UCSP (derate 22mW/°C above +70°C) ...............1.75W

20-Pin 5mm x 5mm x 0.9mm TQFN (derate 20.8mW/°C

above +70°C) (Note 2)...................................................1.67W

36-Bump WLP (derate 22mW/°C above +70°C)............1.75W

Operating Temperature Range ...........................-40°C to +85°C

Maximum Junction Temperature .....................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow)

Lead(Pb)-Free (TQFN, WLP)........................................+260°C

Containing Lead (UCSP)............................................. +240°C

ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input Supply Range

3.0

5.5

V

Maximum TEC Current

±1.5

A

Reference Voltage

1.485

1.500

1.515

V

Reference Load Regulation

1.2

5.0

mV

140

150

160

40

50

60

143

150

155

MAXIP/MAXIN Threshold

Accuracy

45

50

55

mV

0.09

0.14

nFET On-Resistance

0.11

0.16

Ω

0.14

0.23

pFET On-Resistance

0.17

0.30

Ω

°C

0.03

4.00

nFET Leakage

°C

0.3

µA

°C

0.03

4.00

pFET Leakage

°C

0.3

µA

Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to

exceed the IC’s package power dissipation limits.

Note 2: Solders underside metal slug to PCB ground plane.

PACKAGE THERMAL CHARACTERISTICS (Note 3)

20 TQFN

Junction-to-Ambient Thermal Resistance (

Junction-to-Case Thermal Resistance (

6x6 UCSP

Junction-to-Ambient Thermal Resistance (

Junction-to-Case Thermal Resistance (

36 WLP

Junction-to-Ambient Thermal Resistance (

Junction-to-Case Thermal Resistance (

Note 3: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-

layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.