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MAX1437 Datasheet(PDF) 5 Page - Maxim Integrated Products

Part # MAX1437
Description  Octal, 12-Bit, 65Msps, 1.8V ADC with Serial LVDS Outputs Serial LVDS Outputs
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1437 Datasheet(HTML) 5 Page - Maxim Integrated Products

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Octal, 12-Bit, 65Msps, 1.8V ADC
with Serial LVDS Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, external VREFIO = 1.24V, CREFIO = 0.1µF, CREFP = 10µF, CREFN = 10µF,
fCLK = 65MHz (50% duty cycle), VDT = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Note 8)
Data Valid to CLKOUT Rise/Fall
tOD
Figure 5 (Note 9)
(tSAMPLE /24)
- 0.15
(tSAMPLE /24)
+ 0.15
ns
CLKOUT Output-Width High
tCH
Figure 5
tSAMPLE /12
ns
CLKOUT Output-Width Low
tCL
Figure 5
tSAMPLE /12
ns
FRAME Rise to CLKOUT Rise
tCF
Figure 4 (Note 9)
(tSAMPLE /24)
- 0.15
(tSAMPLE /24)
+ 0.15
ns
Sample CLK Rise to FRAME Rise
tSF
Figure 4 (Note 9)
(tSAMPLE /2)
+ 1.1
(tSAMPLE /2)
+ 2.6
ns
Crosstalk
(Note 4)
-85
dB
Gain Matching
CGM
fIN = 5.3MHz (Note 4)
±0.1
dB
Phase Matching
CPM
fIN = 5.3MHz (Note 4)
±0.25
Degrees
Note 2: Specifications at TA ≥ +25°C are guaranteed by production testing. Specifications at TA < +25°C are guaranteed by design
and characterization and not subject to production testing.
Note 3: All capacitances are between the indicated pin and GND, unless otherwise noted.
Note 4: See definition in the
Parameter Definitions section at the end of this data sheet.
Note 5: See the
Common-Mode Output (CMOUT) section.
Note 6: Connect REFADJ to GND directly to enable internal reference mode. Connect REFADJ to AVDD directly to disable the inter-
nal bandgap reference and enable external reference mode.
Note 7: Measured using CREFP to GND = 1µF and CREFN to GND = 1µF. tENABLE time may be lowered by using smaller capacitor values.
Note 8: Data valid to CLKOUT rise/fall timing is measured from 50% of data output level to 50% of clock output level.
Note 9: Guaranteed by design and characterization. Not subject to production testing.
Typical Operating Characteristics
(VAVDD = 1.8V, VOVDD = 1.8V, VCVDD = 3.3V, VGND = 0V, internal reference, differential input at -0.5dBFS, fIN = 5.3MHz, fCLK = 65MHz
(50% duty cycle), VDT = 0V, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
FFT PLOT
(16,384-POINT DATA RECORD)
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
-110
0
5
10
15
20
25
30
fCLK = 65.4966636MHz
fIN = 5.304814MHz
AIN = -0.5dBFS
SNR = 70.120dB
SINAD = 70.112dB
THD = -97.686dBc
SFDR = 95.406dBc
HD2
HD3
FFT PLOT
(16,384-POINT DATA RECORD)
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-90
-110
fCLK = 65.4966637MHz
fIN = 30.313794MHz
AIN = -0.5dBFS
SNR = 69.584dB
SINAD = 69.516dB
THD = -97.316dBc
SFDR = 94.713dBc
HD2
HD3
0
5
10
15
20
25
30
CROSSTALK
(16,384-POINT DATA RECORD)
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-70
-60
-80
-100
-110
-90
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2
fIN(IN1) = 5.304814MHz
fIN(IN2) = 30.3189139MHz
CROSSTALK = 85.4dB
fIN(IN2)
0
5
10
15
20
25
30


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