TCA62746AFG/AFNG

2007-11-27

4

Truth Table

SCK

SLAT

OE

SIN

SOUT

H

L

Dn

Dn

L

L

Dn

No Change

Dn

H

L

Dn

Dn

Dn

- *2

L

Dn

Dn

Dn

- *2

H

Dn

OFF

Dn

Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the

respective output will be OFF.

Note2: “-“is irrelevant to the truth table.

Timing Chart

Note 1:

The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit.

Note 2:

Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set

to “H” the latch circuit does not hold data. The data will instead pass onto output.

When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the

data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data.

SIN

SLAT

SCK

OUT0

OUT1

SOUT

OE

OUT15

H

L

n

1

2

3

4

5

6

8

H

L

H

L

H

L

ON

OFF

ON

OFF

ON

OFF

ON

OFF

H

L

79

11

10

12 13

15

14

2

OUT