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MAX1026 Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX1026 Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 22 page 10-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference 10 ______________________________________________________________________________________ Converter Operation The MAX1026/MAX1028/MAX1030 ADCs use a fully dif- ferential, successive-approximation register (SAR) con- version technique and an on-chip T/H block to convert temperature and voltage signals into a 10-bit digital result. Both single-ended and differential configurations are supported, with a unipolar signal range for single- ended mode and bipolar or unipolar ranges for differ- ential mode. Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequen- cy signals aliasing into the frequency band of interest. Analog Input Protection Internal ESD protection diodes clamp all pins to VDD and GND, allowing the inputs to swing from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. 3-Wire Serial Interface The MAX1026/MAX1028/MAX1030 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode so it generates the serial clock signal. Select the SCLK frequency of 10MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the μP control registers to the same value. The MAX1026/ MAX1028/MAX1030 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. Bipolar true-dif- ferential results and temperature sensor results are available in two’s complement format, while all others are in binary. Serial communication always begins with an 8-bit input data byte (MSB first) loaded from DIN. Send a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see Tables 1, 3, 4, and 5). A high-to-low transition on CS ini- tiates the data input operation. The input data byte and the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK. Tables 1–7 detail the register descriptions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively, control the clock modes in the setup register (see Table 3). Choose between four different clock modes for various ways to start a conversion and determine whether the acquisi- tions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN_ to act as a conver- sion start and use it to request the programmed inter- nally timed conversions without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. Request and start inter- nally timed conversions through the serial interface by writing to the conversion register in the default clock mode, 10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 4–7 for timing specifica- tions and how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the last-requested operation and is waiting for the next input data byte (for clock modes 00 and 10). For clock mode 01, EOC goes low after the ADC completes each requested operation. EOC goes high when CS or CNVST goes low. EOC is always high in clock mode 11. Single-Ended/Differential Input The MAX1026/MAX1028/MAX1030 use a fully differen- tial ADC for all conversions. The analog inputs can be configured for either differential or single-ended con- versions by writing to the setup register (see Table 3). Single-ended conversions are internally referenced to GND (see Figure 3). In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13, and AIN14/AIN15. AIN0–AIN7 are available on the MAX1026, MAX1028, and MAX1030. AIN8–AIN11 are only available on the MAX1028 and MAX1030. AIN12–AIN15 are only available on the MAX1030. See Tables 2–5 for more details on configuring the inputs. For the inputs that can be configured as CNVST or an analog input, only one can be used at a time. For the inputs that can be configured as REF- or an analog input, the REF- configuration excludes the analog input. |
Similar Part No. - MAX1026_11 |
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Similar Description - MAX1026_11 |
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