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R01DS0041EJ0050 Rev.0.50 Page 55 of 90 Apr 15, 2011 RX210 Group 2. CPU Under development Preliminary document Specifications in this document are tentative and subject to change. (2) Pipeline Flow with no Stall (a) Bypass process Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process. Figure 2.22 Bypass Process (b) When WB stages for the memory load and for the operation are overlapped Even when the WB stages for the memory load and for the operation are overlapped, the operation processing is pipelined in, because the load data and the operation result can be written to the register at the same timing. Figure 2.23 When WB Stages for the Memory Load and for the Operation are Overlapped (c) When subsequent instruction writes to the same register before the end of memory load Even when the subsequent instruction writes to the same register before the end of memory load, the operation processing is pipelined in, because the WB stage for the memory load is canceled. Figure 2.24 When Subsequent Instruction Writes to the Same Register before the End of Memory Load IF D E ADD R1, R2 SUB R3, R2 WB IF D E WB Bypass process (mop) add (mop) sub IF D E MOV [R1], R2 IF D E WB ADD R5, R3 M WB (mop) add (mop) load Executed at the same timing even when the WB stages are overlapped IF D E MOV [R1], R2 IF D E WB M WB M IF D E WB IF D E WB (mop) load (Canceled when the register number matches either of them) |
