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R01DS0041EJ0050 Rev.0.50 Page 53 of 90 Apr 15, 2011 RX210 Group 2. CPU Under development Preliminary document Specifications in this document are tentative and subject to change. Figure 2.13 to Figure 2.19 show the operation of instructions that are converted into basic multiple micro-operations. Note: • mop: Micro-operation, stall: Pipeline stall Figure 2.13 Arithmetic/Logic Instruction (Memory Source Operand) Figure 2.14 MOV Instruction (Memory-Memory), Bit Manipulation Instruction (Memory Source Operand) Figure 2.15 EMUL, EMULU Instructions (Register- Register, Register-Immediate) Figure 2.16 XCHG Instruction (Registers) Figure 2.17 XCHG Instruction (Memory Source Operand) IF D E ADD [R1], R2 M1 stall E WB D (mop1) load (mop2) add Bypass process IF D E MOV [R1], [R2] M1 Load data Bit manipulation, store operation (mop1) load (mop2) bit manipulation, store D E M1 M1 IF D E EMUL R2, R4 WB D (mop1) emul-1 (mop2) emul-2 WB Write to R4 Write to R5 E IF D E XCHG R1, R2 D (mop1) xchg-1 Read from/Write to the register (mop2) xchg-2 Write to the register WB E WB IF D E XCHG [R1], R2 D (mop1) load (mop2) store WB E M1 M1 |
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