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PCF212HA Datasheet(PDF) 5 Page - NXP Semiconductors |
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PCF212HA Datasheet(HTML) 5 Page - NXP Semiconductors |
5 / 63 page PCF2123 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 27 April 2011 5 of 63 NXP Semiconductors PCF2123 SPI Real time clock/calendar 7.2 Pin description [1] The die paddle (exposed pad) is wired to VSS and should be electrically isolated. [2] The substrate (rear side of the die) is wired to VSS and should be electrically isolated. Table 3. Pin description Symbol Pin Description HVQFN16 (PCF2123BS/1) TSSOP14 (PCF2123TS/1) PCF2123Ux (bare die) OSCI 16 1 7 oscillator input; high-impedance node; minimize wire length between quartz and package OSCO 1 2 8 oscillator output; high-impedance node; minimize wire length between quartz and package n.c. 6, 7, 14, 15 3, 11 - do not connect and do not use as feed through; connect to VDD if floating pins are not allowed TEST 2 4 9 test pin; not user accessible; connect to VSS or leave floating (internally pulled down) INT 3 5 10 interrupt output (open-drain; active LOW) CE 4 6 11 chip enable input (active HIGH) with internal pull down VSS 5[1] 712[2] ground SDO 8 8 1 serial data output, push-pull; high-impedance when not driving; can be connected to SDI for single wire data line SDI 9 9 2 serial data input; may float when CE is inactive SCL 10 10 3 serial clock input; may float when CE is inactive CLKOE 11 12 4 CLKOUT enable or disable pin; enable is active HIGH CLKOUT 12 13 5 clock output (open-drain) VDD 13 14 6 supply voltage; positive or negative steps in VDD may affect oscillator performance; recommend 100 nF decoupling close to the device (see Figure 29) |
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