PCA9922

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 2 — 6 April 2011

9 of 27

NXP Semiconductors

PCA9922

8-channel constant current LED driver with output error detection

7.2.4 Setting the outputs to test

Before the Capture Fault sequence may be performed, the outputs must be set up. A logic

HIGH must be sent to the output control register for all eight bits. This is done after the

Enter Error Detect sequence is performed as a normal data load sequence as seen in

Figure 5. Please note that this process is completely destructive to the data that is stored

in the output control register (and the LED[7:0] pins). The output control register will have

to be restored to its proper values by the user after the error detect sequence has been

completed.

7.2.5 Capturing the fault/output error data

The Capture Fault/Error Data sequence can only follow the Enter Error Detect sequence.

If the Error Detect sequence has not occurred, this sequence will be treated as a normal

operational sequence. Once the Capture Fault sequence has occurred, an Exit Error

Detect sequence should be performed. There can be no more Capture Sequences until

another Enter Error Detect sequence has occurred.

The Capture Fault Sequence consists of holding OE LOW for no less than 3 clocks (CLK)

and for a minimum of 2

μs, whichever is longer. During this period of time, the shift register

is being loaded with the fault status. As such, data presented to the device via SDI will not

be captured. Bit 7 of the fault data will be present on SDO by the first falling edge CLK

after the user de-asserts OE for this cycle. An error condition is output as a 1 (HIGH bit),

and a 0 (LOW bit) designates a normal status. Timing for this sequence is shown in

Figure 7.

Fig 7.

Timing for ‘Capture Fault Mode’ command

CLK

LE

OE

002aad205

OE = 1'b0 for minimum of 3 clocks

or 2

μs, whichever is longer

SDO

previous serial data

fault data MSB

resume shift

with fault data