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LPC11U12FHN201 Datasheet(PDF) 10 Page - NXP Semiconductors |
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LPC11U12FHN201 Datasheet(HTML) 10 Page - NXP Semiconductors |
10 / 64 page LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 — 11 April 2011 10 of 64 NXP Semiconductors LPC11U1x 32-bit ARM Cortex-M0 microcontroller TMS/PIO0_12/AD1/ CT32B1_CAP0 22 33 C7 [6] I; PU I TMS — Test Mode Select for JTAG interface. -I/O PIO_12 — General purpose digital input/output pin. -I AD1 — A/D converter, input 1. -I CT32B1_CAP0 — Capture input 0 for 32-bit timer 1. TDO/PIO0_13/AD2/ CT32B1_MAT0 23 34 C8 [6] I; PU O TDO — Test Data Out for JTAG interface. -I/O PIO0_13 — General purpose digital input/output pin. -I AD2 — A/D converter, input 2. -O CT32B1_MAT0 — Match output 0 for 32-bit timer 1. TRST/PIO0_14/AD3/ CT32B1_MAT1 24 35 B7 [6] I; PU I TRST — Test Reset for JTAG interface. -I/O PIO0_14 — General purpose digital input/output pin. -I AD3 — A/D converter, input 3. -O CT32B1_MAT1 — Match output 1 for 32-bit timer 1. SWDIO/PIO0_15/AD4/ CT32B1_MAT2 25 39 B6 [6] I; PU I/O SWDIO — Serial wire debug input/output. -I/O PIO0_15 — General purpose digital input/output pin. -I AD4 — A/D converter, input 4. -O CT32B1_MAT2 — Match output 2 for 32-bit timer 1. PIO0_16/AD5/ CT32B1_MAT3/WAKEUP 26 40 A6 [6] I; PU I/O PIO0_16 — General purpose digital input/output pin. -I AD5 — A/D converter, input 5. -O CT32B1_MAT3 — Match output 3 for 32-bit timer 1. -I WAKEUP — Deep power-down mode wake-up pin with 20 ns glitch filter. This pin must be pulled HIGH externally to enter Deep power-down mode and pulled LOW to exit Deep power-down mode. A LOW-going pulse as short as 50 ns wakes up the part. PIO0_17/RTS/ CT32B0_CAP0/SCLK 30 45 A3 [3] I; PU I/O PIO0_17 — General purpose digital input/output pin. -O RTS — Request To Send output for USART. -I CT32B0_CAP0 — Capture input 0 for 32-bit timer 0. -I/O SCLK — Serial clock input/output for USART in synchronous mode. Table 3. Pin description Symbol Reset state [1] Type Description |
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