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LPC11U12FHN201 Datasheet(PDF) 2 Page - NXP Semiconductors |
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LPC11U12FHN201 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 64 page LPC11U1X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Objective data sheet Rev. 1 — 11 April 2011 2 of 64 NXP Semiconductors LPC11U1x 32-bit ARM Cortex-M0 microcontroller Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins. High-current source output driver (20 mA) on one pin (P0_7). High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5). Four general purpose counter/timers with a total of up to 5 capture inputs and 13 match outputs. Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal low-power WatchDog Oscillator (WDO). Analog peripherals: 10-bit ADC with input multiplexing among eight pins. Serial interfaces: USB 2.0 full-speed device controller. USART with fractional baud rate generation, internal FIFO, a full modem control handshake interface, and support for RS-485/9-bit mode and synchronous mode. USART supports an asynchronous smart card interface (ISO 7816-3). Two SSP controllers with FIFO and multi-protocol capabilities. I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode. Clock generation: Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator). 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a system clock. Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable frequency output. PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources. A second, dedicated PLL is provided for USB. Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control: Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Power profiles residing in boot ROM allow optimized performance and minimized power consumption for any given application through one simple function call. Processor wake-up from Deep-sleep and Power-down modes via reset, selectable GPIO pins, watchdog interrupt, or USB port activity. Processor wake-up from Deep power-down mode using one special function pin. Integrated PMU (Power Management Unit) to minimize power consumption during Sleep, Deep-sleep, Power-down, and Deep power-down modes. Power-On Reset (POR). Brownout detect with four separate thresholds for interrupt and forced reset. Unique device serial number for identification. Single 3.3 V power supply (1.8 V to 3.6 V). Temperature range −40 °C to +85 °C. Available as 48-pin LQFP, 48-pin TFBGA, and 33-pin HVQFN package. Pin compatible to the LPC134x series. |
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