HEF40175B

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 7 — 3 May 2011

3 of 15

NXP Semiconductors

HEF40175B

Quad D-type flip-flop

6.

Pinning information

6.1 Pinning

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

↑ = positive-going transition; ↓ = negative-going transition.

Fig 3.

Pin configuration SOT38-4 and SOT109-1

Fig 4.

Pin configuration SOT403-1

HEF40175B

MR

Q0

Q3

Q0

Q3

D0

D3

D1

D2

Q1

Q2

Q1

Q2

CP

001aae570

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

HEF40175B

MR

Q0

Q3

Q0

Q3

D0

D3

D1

D2

Q1

Q2

Q1

Q2

CP

001aan211

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Table 2.

Pin description

Symbol

Pin

Description

MR

1

master reset input (active LOW)

Q0 to Q3

2, 7, 10, 15

buffered output

Q0 to Q3

3, 6, 11, 14

complementary buffered output

D0 to D3

4, 5, 12, 13

data input

8

ground supply voltage

CP

9

clock input (LOW-to-HIGH edge-triggered)

16

supply voltage

Table 3.

Function table [1]

Input

Output

CP

Dn

MR

Qn

Qn

↑

HHHL

↑

LH

LH

↓

X

H

no change

no change

XXL

L

H