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FAN7389 Datasheet(PDF) 7 Page - Fairchild Semiconductor

Part # FAN7389
Description  3-Phase Half-Bridge Gate-Drive IC
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN7389 Datasheet(HTML) 7 Page - Fairchild Semiconductor

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© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7389 • Rev. 1.0.0
7
Electrical Characteristics
VBIAS (VDD, VBS1,2,3) = 15.0V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to
COM and are applicable to all six channels. The VO and IO parameters are referenced to VS1,2,3 and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The VDDUV parameters are referenced to COM. The
VBSUV parameters are referenced to VS1,2,3.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Over-Current Protection Section
VCSTH+
Over-Current Detect Positive Threshold
(5)
400
500
600
mV
VCSTH-
Over-Current Detect Negative Threshold
(5)
440
mV
VCSHYS
Over-Current Detect Hysteresis
(5)
60
mV
ICSIN
Short-Circuit Input Current
VCSIN=1V
5
10
15
μA
ISOFT
Soft Turn-Off Sink Current
25
40
55
mA
Fault Output Section
VRCINTH+ RCIN Positive-Going Threshold Voltage
3.3
V
VRCINTH- RCIN Negative-Going Threshold Voltage
2.6
V
VRCINHYS RCIN Hysteresis Voltage
0.7
V
IRCIN
RCIN Internal Current Source
CRCIN=2nF
3
5
7
µA
VFOL
Fault Output Low Level Voltage
VCS=1V, IFO=1.5mA
0.2
0.5
V
RDSRCIN RCIN On Resistance
IRCIN=1.5mA
50
75
100
Ω
RDSFO
Fault Output On Resistance
IFO=1.5mA
90
130
170
Ω
Note:
5.
These parameters are guaranteed by design.
Dynamic Electrical Characteristics
TA=25°C, VBIAS (VDD, VBS1,2,3) = 15.0V, VS1,2,3 = COM, and CLoad = 1000pF unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max.
Unit
tON
Turn-On Propagation Delay
VLIN1,2,3=VHIN1,2,3=0V, VS1,2,3=0V
350
500
650
ns
tOFF
Turn-Off Propagation Delay
VLIN1,2,3=VHIN1,2,3=5V, VS1,2,3=0V
350
500
650
ns
tR
Turn-On Rise Time
VLIN1,2,3=VHIN1,2,3=0V
20
50
100
ns
tF
Turn-Off Fall Time
VLIN1,2,3=VHIN1,2,3=5V
10
30
80
ns
tEN
Enable LOW to Output Shutdown Delay
400
500
600
ns
tCSBLT
CS Pin Leading-Edge Blanking Time
(6)
200
300
400
ns
tCSFO
Time from CS Triggering to
From VCSC=1V to
Turn-Off
630
ns
tCSOFF
Time from CS Triggering to All Gate
Outputs Turn-Off
From VCSC=1V to Starting Gate
Turn-Off
640
ns
tFLT,IN
Input Filtering Time
(7) (HINx, LINx)
200
250
300
ns
Input Filtering Time
(7) (EN)
200
250
300
ns
tFLTCLR
Fault-Clear Time
RCIN: CRCIN=2nF
1.3
ms
DT
Dead Time
250
300
350
ns
MDT
Dead-Time Matching (All Six Channels)
50
ns
MT
Delay Matching (All Six Channels)
50
ns
PM
Output Pulse-Width Matching
(6,8)
PWIN > 1µs
50
100
ns
Notes:
6.
These parameters are guaranteed by design.
7.
The minimum width of the input pulse should exceed 500ns to ensure the filtering time of the input filter is exceeded.
8.
PM is defined as PWIN-PWOUT,
FO
FO


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