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EEFUE0G181R Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part # EEFUE0G181R
Description  Dual DDR / Dual-Output PWM Controller
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

EEFUE0G181R Datasheet(HTML) 3 Page - Fairchild Semiconductor

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© 2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5026 • Rev. 1.0.8
3
Pin Configuration
Figure 3. TSSOP-28
Pin Definitions
Pin #
Name
Description
1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin
2
LDRV1
Low-Side Drive. The low-side (lower) MOSFET driver output. Connect to gate of low-side
MOSFET.
27
LDRV2
3
PGND1
Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side
MOSFET.
26
PGND2
4
SW1
Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect
to source of high-side MOSFET and low-side MOSFET drain.
25
SW2
5
HDRV1
High-Side Drive. High-side (upper) MOSFET driver output. Connect to gate of high-side
MOSFET.
24
HDRV2
6
BOOT1
BOOT. Positive supply for the upper MOSFET driver. Connect as shown in Figure 4.
23
BOOT2
7
ISNS1
Current-Sense Input. Monitors the voltage drop across the lower MOSFET or external sense
resistor for current feedback.
22
ISNS2
8
EN1
Enable. Enables operation when pulled to logic HIGH. Toggling EN resets the regulator after a
latched fault condition. These are CMOS inputs whose state is indeterminate if left open.
21
EN2
9
GND
Ground
20
10
VSEN1
Output Voltage Sense. The feedback from the outputs; used for regulation as well as PG,
under-voltage, and over-voltage protection and monitoring.
19
VSEN2
Continued on the following page…


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