APP NOTE NUMBER

APPLICATION NOTE

© 2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.0 • 7/14/09

2

Power Loss Measurement

Figure 2 shows the power loss diagram of a Fairchild

DrMOS evaluation board. The input powers are PIN, PCIN

and PDRV. Output power of the module is PSW. POUT is

total board output power after power loss of the inductor.

POUT is connected to Load.

Figure 2. Ploss Diagram of FDMF6704 Eval Board

When designing a Sync Buck application, critical design

parameters are input/output voltage, output current,

switching frequency and inductor value. Typically input and

output voltages are decided by the system application.

Switching frequency and output inductor are then optimized

to get the best trade-off among dynamic performance, EMI,

thermal, BOM, cost, etc.

Using module power loss as a figure of merit, it is easy to

judge which DrMOS design point is better or not since the

module power loss does not include the inductor power

loss. In other words, even using different inductors, module

power loss can specify the real and accurate power loss of

module itself and it is only slightly affected by inductor

power loss, if the inductor value is correct and the

application design is optimized.

PIN

VIN x IIN [W]

PCIN&PDRV

VCIN x ICIN [W] (including PDRV)

PSW

VSW x IOUT [W]

POUT

VOUT x IOUT [W]

PLmodule

PIN + PCIN&PDRV – PSW [W]

PLinductor

PSW – POUT [W]

Efficiency@SW

PSW/(PIN+PCIN&PDRV)*100 [%]

Efficiency@Out

POUT/(PIN+PCIN&PDRV)*100

[%]

Table 1. Power, Power Loss and Efficiency

Total

Pin

[W]

PLmod

[W]

Psw

[W]

PLind

[W]

Pout

[W]

Effi

@SW

[%]

Effi

@Out

[%]

46.49

6.771

39.72

0.64

39.08

85.44

84.06

Table 2. Power Loss Example at 30A Load

Table 1 and Table 2 show an example of power loss

definition, measurement and calculation. A Fairchild

FDMF6704 evaluation board was used for the testing. Note

that module power loss without inductor power loss makes

SW node efficiency higher than output node efficiency.

Inductor power loss is 0.64 W and it makes output

efficiency 1.3 % lower than SW node efficiency. If the

inductor value is not optimized, the whole system

performance as well as DrMOS will be affected and

decreased. All input/output voltage and current are

measured with precise DMM and current shunt resistors for

accurate data capture.

Power Loss Graph in Datasheet

The evaluation board total efficiency, SW node efficiency

and module power loss are measured and calculated to

represent DrMOS product performance in the datasheet.

The FDMF6704 datasheet has several graphs which indicate

module power loss, output current, normalized module

power loss and each design parameter variations. Figure 3

shows an example of a graph in the datasheet for module

power loss vs. output current.

Figure 3. Module Power Loss vs. Iout

Figure 3 represents a performance of FDMF6704 with

particular parameter values, such as VIN=12 V, VOUT=1.3

V, LOUT=440 nH, Fsw=350 kHz and output current from 0

to 35 A. This graph shows a performance under specific

condition. In order to use the datasheet graphs easily in

various system designs, normalized power loss graphs for

each key parameter are included in the datasheet. In the

Figure 4, power loss of the module is plotted with a

normalized value according to the output voltage change.

The reference value of module power loss for normalization

is chosen as 1.3 Vout because this voltage is typical in a

computing application, such as multi-phase VRD for Vcore.

When the output voltage is 2 V, normalized module power

loss will be around 1.13 times higher compared to 1.3 Vout.

Psw

Pout

DrMOS

FDMF

6704

Pin

Output

Inductor

Pcin&

Pdrv

PLinductor

Effi@SW

Effi@Out

Load

PLmodule