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AN-9046 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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AN-9046 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
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2 / 10 page  is recommended the customer follow this recommended footprint to assure best assembly yield, thermal performance and overall system performance. PAD FINISH The dual Power56 is sold with a NiPdAu lead free lead finish. Immersion silver, immersion nickel gold and organic surface protectant, OSP are the pad finishes of choice for lead free processing. Each finish has useful properties, and each has its challenges. It is beyond the scope of this paper to debate each system’s merits. No one finish will be right for all applications, but currently the most commonly seen in large scale consumer electronics, largely due to cost, is OSP. A high quality OSP, formulated for the rigors of lead free reflow, like Enthone ® Entek® Plus HT is recommended. PWB MATERIAL It is recommended that lead free FR-4 is used in PWB construction. Lower quality FR-4 can cause numerous problems with the reflow temperatures seen when using lead free solder. IPC-4101B “Specification for Base Materials for Rigid and Multilayer Printed Boards” contains further information on choosing the correct PWB material for the intended application. USING VIAS WITH DUAL POWER56 Often the designer will wish to place vias inside of the thermal pads. While this is acceptable, the user should realize that vias often create voiding, and is advised to carefully characterize the PWB and process designs with x-ray inspection to ensure there is not a voiding problem. There are several types of vias that can be used in PWB design. Blind vias are not recommended due to the fact they often trap gases generated during reflow and yield high percentages of voiding. Solder mask can also be placed over the top of the via to prevent solder from wicking down the via. It has been shown in previous studies that this will create a higher incidence of voiding than an open through- hole or filled via. If through hole vias are used, a drill size of 0.3mm with 1 ounce copper plating yields good performance. With through-hole vias, solder wicking through the hole, or solder protrusion, must be considered. In high reliability applications, filled vias are the preferred due to lower incidences of voiding during reflow. The user can expect this approach to eliminate the stress riser created by a void at the edges of the via barrel. STENCIL DESIGN It is estimated that 60% of all assembly errors are due to paste printing. For a controlled, high yielding manufacturing process, it is therefore the most critical phase of assembly. Due to the importance of the stencil design, many stencil types have been characterized to determine the optimal stencil design for the recommended footprint pad, on a typical application board with Organic Surface Protectant (OSP) surface finish, thermal vias, on FR-4. Solder paste coverage for the thermal pads was printed ranging from 50-65% coverage. To allow gases to escape during reflow it is recommended that the paste be deposited in a grid allowing “channels” for gases to vent. It was found that 40-60% solder coverage on the large “S1/D2” pad yielded good void performance, while maintaining good standoff height. The paste was printed from a 5 mil thick stainless steel stencil. Various different stencil apertures shapes can be used, but were not studied here. The paste is printed on the outer pins with a slightly reduced ratio to the PWB pad. Per IPC-7525 “Stencil Design Guidelines” gives a formula for calculating the area ratio for paste release prediction: T W L W L Walls Aperture of Area Pad of Area Ratio Area * ) * ( * 2 * = = Where L is the length, W the width, and T the thickness of the stencil. When using this equation, an Area Ratio >0.66 should yield acceptable paste release. The recommended stencil apertures can be found in the appendix. |
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