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AN-8021 Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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AN-8021 Datasheet(HTML) 8 Page - Fairchild Semiconductor |
8 / 13 page AN-8021 APPLICATION NOTE © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.1 • 6/1/10 8 A few other problems, which should be seriously considered when the output levels are selected, are the amplitude of the line frequency ripple voltage across the converter’s output capacitor and hold-up time requirements. The issue is that energy stored in the capacitor is proportional to the square of the output voltage. Assume that the output capacitor is calculated for 400V output and +/-20V (i.e. +/-5%) line frequency ripple at full load. At 300V output, the ripple would grow to +/-35V (or +/-12%) and, at 200V, it would reach +/-80V (equal to +/-40%). Generally, the lower the output voltage set point is, especially VOUT,L, the output capacitance of the converter must be significantly over designed to keep the line frequency ripple under control. Similarly, meeting the hold-up time requirement at a drastically lowered output voltage level imposes a severe penalty in output capacitance. Once the suitable output voltages are established, the circuit diagram shown in Figure 13 can be used to implement a two-level boost power factor corrector. The circuit implementation includes two sections, R8, R9 and the “ideal, sink-only diode” comprised of U1 and D1 is used to establish the VOUT,L voltage level. In the other section of the circuit, U2 is configured as a comparator, where its threshold for the output voltage switchover is determined by R11 and R12. The transistor Q1 and R13 provides hysteresis for the comparator. The output of the comparator, together with D2, R10 current limiting resistor, and C3 filter capacitor; is used to override the voltage presented at the non-inverting input of U1. Once the peak input voltage exceeds the desired value corresponding to VIN,SW, the comparator output goes HIGH and peak charges C3 filter capacitor to approximately a diode forward voltage drop less than U2’s 5V bias voltage. At that point, D1 becomes reverse biased and CSS is charged to its nominal 3V level, which corresponds to the nominal output voltage of the converter, VOUT,H. The wide hysteresis established by R13 and Q1 ensures that the output of U2 remains HIGH for approximately one quarter of a line period to be able to charge C3 to the final voltage level at the first trigger event of the comparator. The design procedure of this circuit starts by setting VOUT,L. The lower output voltage level is established by R8 and R9 and these resistors, together with R10 and C3, also define the time constant of the comparator’s output filter. The impedance has to be quite high to reduce the C3 capacitor value. It is recommended to set the divider current to 10µA, which means: 500kΩ 10μ0 5V R9 R8 = = + (19) Figure 13. Two-Level Boost Output Voltage Implementation |
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