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SG6902 Datasheet(PDF) 7 Page - Fairchild Semiconductor |
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SG6902 Datasheet(HTML) 7 Page - Fairchild Semiconductor |
7 / 12 page AN-6902 APPLICATION NOTE © 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.2.1 • 5/1/08 7 Figure 9. Multi-vector Error Amplifier Equation 22 shows the output of the voltage error amplifier, VEA, controls the total input power and the power delivered to the load. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of PFC output voltage. Figure 10 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage (FBPFC) exceeds ±5% of the reference voltage (3V), the trans-conductance error amplifier programs its output current to speed up the loop response. If RA is open circuit, SG6902 is turned off immediately to prevent over-voltage on the output capacitor. Two-level PFC Output voltage For universal input (90VAC ~ 264VAC), the output voltage of PFC is usually designed to 250V at low line and 400V at high line. This improves efficiency of the power converter for low-line input. The RANGE pin (open- drain) is used for the two-level output voltage setting. Figure 10 shows the RANGE output that programs the PFC output voltage. The RANGE output is shorted to ground when the VRMS voltage exceeds 1.95V. It is a high-impedance output (open) whenever the VRMS voltage drops below 1.6V. The output voltages can be determined using below equations: V 3 R R R V Open Range B B A O × + = ⇒ = (23) () () V 3 R // R R // R R V GND Range C B C B A O × + = ⇒ = (24) Determine the resistor divider ratio RA/RB: 1 3 V R R O B A − = (25) 33 . 82 1 3 250 R R B A = − = (26) Assume RA = 3MΩ, RB = 36.5KΩ, and RC = 60KΩ. Refer to Figure 10. At high line input, maximum output voltage is: V 420 1 R // R R 15 . 3 V C B A ) MAX ( O = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + = × = (27) Another circuit provides further over-voltage protection to inhibit the PFC switching once the feedback voltage exceeds the 3.25V the output voltage is clamped at: V 433 1 R // R R 25 . 3 V C B A ) OVP ( O = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ + × = (28) Figure 10. Feedback Voltage of PFC PWM SECTION Soft-starting the PWM stage The soft-start pin controls the rising time of the output voltage and prevents the overshoot during power on. The soft-start capacitor value for the soft-start period tSS is given by: OZ SS SS SS V I t C × = (29) where VOZ is the zero-duty threshold of FBPWM voltage. VO RB RC RA VEA FBPFC RANGE 3V + SG69XX (PFC) |
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