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FAN9611 Datasheet(PDF) 9 Page - Fairchild Semiconductor |
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FAN9611 Datasheet(HTML) 9 Page - Fairchild Semiconductor |
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9 / 18 page  AN-6086 © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com Rev. 1.0.4 • 4/22/10 9 (Design Example) Setting the limited output power as 120% of nominal output power, the maximum on time is given as: ,, , 22 ,, 6 2 2( ) 2 (1.2 200) 2 202 10 14.1 85 0.95 MAX CH MAX OUT CH ON MAX LINE MIN LINE MIN P LK P L t VV s ηη μ − ⋅⋅ ⋅ == ⋅⋅ ⋅⋅ ⋅ × == ⋅ Then, the resistor on MOT pin is obtained as: ,IN2 , 2 12 IN1 IN2 6 2 12 2 () 230 10 14.1 10 18.9 2 85 () 78 18.9 2000 230 10 ON MAX LINE MIN MOT tR V R RR k − − − = + × ×⋅ ⋅ == Ω + × The maximum flux density during overload condition is obtained as: 6 , max 6 71.2 202 10 161 10 30 0.35 LPK MAX e BOOST IK L B AN tesla − − ⋅⋅ ⋅⋅ × == ⋅ ×⋅ = [STEP-5] Design Feedback Circuit To regulate the output voltage to a desired value, the voltage divider for feedback should be designed to result in 3V to the feedback (FB) pin, expressed as: 2 12 3 FB OUT FB FB R VV RR ⋅= + (21) (Design Example) Selecting RFB1 as 1MΩ, RFB2 is obtained as: 6 1 2 110 7.56 400 1 1 3 3 FB FB OUT R R k V × == = Ω − − [STEP-6] Design OVP Circuit FAN9611/12 has two levels of over-voltage protection (OVP) for the output. Non-latching OVP is combined with the feedback (FB) pin and trips when the output voltage exceeds 108% of its nominal value. The latching OVP uses dedicated pin and trips when the OVP pin voltage exceeds an independent threshold of 3.5V, expressed as: 2 , 12 3.5 FB OUT LATCH FB FB R VV RR ⋅= + (22) When the latching OVP is combined with FB pin, it trips at 115% of the nominal output voltage. (Design Example) Selecting OVP level as 472V and ROV1 as 2MΩ, ROV2 is obtained as: 6 1 2 , 210 14.9 472 1 1 3.5 3.5 OV OV OUT LATCH R R k V × == = Ω − − [STEP-7] Determine current sensing resistor It is typical to set the pulse-by-current limit level a little higher than the maximum inductor current at maximum power limit condition as: , , , 22 MAX CH CS LIM LINE MIN P I V η ≥⋅ ⋅ (23) Then, the sensing resistor is selected as: . 0.2 CS CS LIM R I = (24) (Design Example) , , , 200 1.2 22 2 2 8.4 85 0.95 MAX CH CS LIM LINE MIN P I A V η ⋅ ≥⋅ = ⋅ = ⋅⋅ Choosing ICS.LIM as 9.1A (10% margin on 8.4A), the sensing resistor is selected as: . 0.2 0.2 0.022 9.1 CS CS LIM R I = == Ω [STEP-8] Output Capacitor Selection The output voltage ripple should be considered when selecting the output capacitor. Figure 16 shows the twice line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: , 2 OUT OUT LINE OUT RIPPLE I C fV π > ⋅⋅ (25) where IOUT is total nominal output current of two boost PFC stage and VOUT,RIPPLE is the peak-to-peak output voltage ripple specification. Since too large ripple on the output voltage may cause premature OVP during normal operation, the peak-to-peak ripple specification should be smaller than 15% of the nominal output voltage. The holdup time also should be considered when determining the output capacitor as: 22 , 2 OUT HOLD OUT OUT OUT MIN Pt C VV ⋅ > − (26) where: POUT is total nominal output power of two boost PFC stage (2POUT,CH); tHOLD is the required holdup time; and VOUT,MIN is the allowable minimum output voltage during the holdup time. |
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