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4

FIGURE 4. PC Board Pin Distribution

FIGURE 5. PC Board Power Planes

Inductance is always present in any conductor. As the rate

of change in current through an inductor increases, the

greater the induced voltage will be since V

= L(di/dt). With

digital systems changing logic levels, a change in current

will inevitably occur and produce unwanted voltage drops.

Oscillations are also connected with additional inductance

present in digital circuits. This implies that inductance in

board design should be kept at a minimum.

Inductance is very dependant on geometry, with solid sheet

conductors being the best for keeping inductance at the

lowest possible level. This is the reason why planes (as in

Figure 5) instead of grids, combs, or traces are used for

power and ground. It is best to mount IC’s directly over

ground planes and connect the device ground pins to it

whenever possible. It is also recommended that decoupling

capacitors of 0.01

µF to 0.1 µF be placed between V

The power required for different IC’s will vary, meaning that

the heat dissipated by each will change. In order to main-

tain gate junction temperatures, cooling devices may be

necessary. As an example, planes can be used as thermal

mass resulting in an effective heat sink. Cooling is impor-

tant because if junction temperatures exceed manufacturer

specifications, circuits can fail, degrade, or function incor-

rectly.

SYSTEM DESIGN CONSIDERATIONS

Wired-OR Configuration

F100K 300 Series devices have an emitter follower config-

uration on each output. The open emitter outputs of several

devices can be tied together to create a Wired-OR configu-

ration. An example of this is shown in Figure 6. This config-

uration has the advantage of obtaining the OR operation

without using an external gate, thus reducing the package

count of the design. The Wired-OR also saves on power by

LAYER 1

Signal

LAYER 2

TTL Ground

LAYER 3

TTL

+5V

LAYER 4

LAYER 5

Signal/Thermal

LAYER 6

ECL

−4.5V (V

LAYER 7

LAYER 8

Signal