Micrel, Inc.

SY87725L

July 2007

11

M9999-071007-B

Symbol

Parameter

Condition

Min

Typ

Max

Units

SIN Maximum Data Rate

2.5

Gbps

1.25

Gbps

Acquisition Lock Time

15

µs

Frequency Difference, LFIN

shows Out-of-Lock

1000

ppm

REFCLK Pulse Width HIGH Time

2.5

ns

REFCLK Pulse Width LOW Time

2.5

ns

Parallel CLKOUT to Parallel Data

Out Skew

See “Figure 1”

-150

+150

ps

CML Output Rise/Fall Time

(20% to 80%)

At full output swing

40

70

100

ps

LVDS Output Rise/Fall Time

(20% to 80%)

At full output swing

100

250

400

ps

CLKOUT, CLKOUT2 Duty Cycle

45

55

%

Note:

6.

The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.