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KS8721SL Datasheet(PDF) 7 Page - Micrel Semiconductor |
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KS8721SL Datasheet(HTML) 7 Page - Micrel Semiconductor |
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7 / 35 page  Micrel, Inc. KS8721BL/SL June 2009 7 M9999-062509-1.3 Pin Description Pin Number Pin Name Type (1) Pin Function 1 MDIO I/O Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K pull-up resistor. 2 MDC I MII Clock Input. This pin is synchronous to the MDIO. 3 RXD3/ PHYAD Ipd/O MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping Options” section for details. 4 RXD2/ PHYAD2 Ipd/O MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping Options” section for details. 5 RXD1/ PHYAD3 Ipd/O MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See “Strapping Options” section for details. 6 RXD0/ PHYAD4 Ipd/O MII Receive Data Output. During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See “Strapping Options” section for details. 7 VDDIO P Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See “Circuit Design Ref. for Power Supply" section for details. 8 GND Gnd Ground. 9 RXDV/ CRSDV/ PCS_LPBK Ipd/O MII Receive Data Valid Output. During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping Options” section for details. 10 RXC O MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output. During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See “Strapping Options” section for details. 12 GND Gnd Ground. 13 VDDC P Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section for details. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ REFCLK I/O MII Transmit Clock Output. Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave XO pin unconnected. 16 TXEN Ipd MII Transmit Enable Input. 17 TXD0 Ipd MII Transmit Data Input. 18 TXD1 Ipd MII Transmit Data Input. 19 TXD2 Ipd MII Transmit Data Input. 20 TXD3 Ipd MII Transmit Data Input. 21 COL/ RMII Ipd/O MII Collision Detect Output. During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping Options” section for details. 22 CRS/ RMII_BTB Ipd/O MII Carrier Sense Output. During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when RMII mode is selected. See “Strapping Options” section for details. 23 GND Gnd Ground. |
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