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KS8721B Datasheet(PDF) 7 Page - Micrel Semiconductor |
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KS8721B Datasheet(HTML) 7 Page - Micrel Semiconductor |
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7 / 32 page  March 2006 7 M9999-030106 KS8721B/BT Micrel, Inc. Pin Number Pin Name Type(Note 1) Pin Function 25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up PHYAD0 /reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB RMII_BTB during reset when RMII mode is selected. See “Strapping Options” section “Strapping Options” “Strapping Options” for details. 23 GND GND Ground. 26 LED0/TEST Ipu/O Link/Activity LED Output: Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See “Strapping Options” section for details. “Strapping Options” “Strapping Options” noFEF Speed Pin State LED Definition 10BT H “off” 100BT L “on” 28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ DUPLEX reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” Duplex Pin State LED Definition Half H “off” Full L “on” 29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ NWAYEN reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” Collison Pin State LED Definition No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See “100BT FX Mode” section for more details. “100BT FX Mode” “100BT FX Mode” 35 GND GND Ground. 36 GND GND Ground. Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect 25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up PHYAD0 /reset. See 22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB RMII_BTB during reset when RMII mode is selected. See for details. 23 GND GND Ground. 26 LED0/TEST Ipu/O Link/Activity LED Output: Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See noFEF Speed Pin State LED Definition 10BT H “off” 100BT L “on” 28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ DUPLEX reset. See Half H “off” Full L “on” 29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ NWAYEN reset. See No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See 35 GND GND Ground. 36 GND GND Ground. Pin Number Pin Name Type 25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up PHYAD0 /reset. See 22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB RMII_BTB during reset when RMII mode is selected. See for details. 23 GND GND Ground. 26 LED0/TEST Ipu/O Link/Activity LED Output: Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See noFEF Speed Pin State LED Definition 10BT H “off” 100BT L “on” 28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ DUPLEX reset. See Half H “off” Full L “on” 29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ NWAYEN reset. See No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See 35 GND GND Ground. 36 GND GND Ground. Pin Number Pin Name Type 25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up PHYAD0 /reset. See 22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB RMII_BTB during reset when RMII mode is selected. See for details. 23 GND GND Ground. 26 LED0/TEST Ipu/O Link/Activity LED Output: Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See noFEF Speed Pin State LED Definition 10BT H “off” 100BT L “on” 28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ DUPLEX reset. See Half H “off” Full L “on” 29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ NWAYEN reset. See No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See 35 GND GND Ground. 36 GND GND Ground. Pin Function 25 INT#/ Ipu/O Management Interface (MII) Interrupt Out: Latched as PHYAD[0] during power up PHYAD0 /reset. See 22 CRS/ Ipd/O MII Carrier Sense Output: The pull-up/pull-down value is latched as RMII BTB RMII_BTB during reset when RMII mode is selected. See for details. 23 GND GND Ground. 26 LED0/TEST Ipu/O Link/Activity LED Output: Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” The external pull-down enable test mode and only used for the factory test. 27 LED1/ Ipu/O Speed LED Output: Latched as SPEED (Register 0, bit 13) during power-up/reset. SPD100/ See Speed Pin State LED Definition 10BT H “off” 100BT L “on” 28 LED2/ Ipu/O Full-duplex LED Output: Latched as DUPLEX (register 0h, bit 8) during power-up/ DUPLEX reset. See Half H “off” Full L “on” 29 LED3/ Ipu/O Collision LED Output: Latched as ANEG_EN (register 0h, bit 12) during power-up/ NWAYEN reset. See No Collision H “off” Collision L “on” 30 PD# Ipu Power Down. 1 = Normal operation, 0=Power down, Active low. 31 VDDRX Pwr Analog 2.5V power supply. 32 RX- I Receive Input: Differential receive input pins for FX, 100BaseTX or 10BaseT. 33 RX+ I Receive Input: Differential receive input pin for FX, 100BaseTX or 10BaseT. 34 FXSD/FXEN Ipd/O Fiber Mode Enable / Signal Detect in Fiber Mode. If FXEN = 0, FX mode is disable. The default is “0”. See 35 GND GND Ground. 36 GND GND Ground. Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” Lnk/Act Pin State LED Definition No Link H “off” Link L “on” Act — “Toggle” Speed Pin State LED Definition 10BT H “off” 100BT L “on” Speed Pin State LED Definition 10BT H “off” 100BT L “on” Duplex Pin State LED Definition Half H “off” Full L “on” Duplex Pin State LED Definition Half H “off” Full L “on” Collison Pin State LED Definition No Collision H “off” Collision L “on” Collison Pin State LED Definition No Collision H “off” Collision L “on” |
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