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KS8721B Datasheet(PDF) 6 Page - Micrel Semiconductor |
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KS8721B Datasheet(HTML) 6 Page - Micrel Semiconductor |
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6 / 32 page  KS8721B/BT Micrel, Inc. M9999-030106 6 March 2006 Pin Description Pin Number Pin Name Type(Note 1) (Note 1) Pin Function 1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up resistor. 2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface 3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See “Strapping Options” section for “Strapping Options” “Strapping Options” details. 4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] PHYAD2 during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] PHYAD3 during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] PHYAD4 during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as CRSDV/ pcs_lpbk during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. REFCLK 16 TXEN Ipd MII Transmit Enable Input 17 TXD0 Ipd MII Transmit Data Input 18 TXD1 Ipd MII Transmit Data Input 19 TXD2 Ipd MII Transmit Data Input 20 TXD3 Ipd MII Transmit Data Input 21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See “Strapping Options” section for details. “Strapping Options” “Strapping Options” 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. Note 1. Pwr = power supply GND = ground I = input O = output I/O = bi-directional Gnd = ground Ipu = input w/ internal pull-up Ipd = input w/ internal pull-down Ipd/O = input w/ internal pull-down during reset, output pin otherwise Ipu/O = input w/ internal pull-up during reset, output pin otherwise PU = strap pin pull-up PD = strap pin pull-down NC = No connect 1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up resistor. 2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface 3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See details. 4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] PHYAD2 during reset. See 5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] PHYAD3 during reset. See 6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] PHYAD4 during reset. See 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as CRSDV/ pcs_lpbk during reset. See PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. REFCLK 16 TXEN Ipd MII Transmit Enable Input 17 TXD0 Ipd MII Transmit Data Input 18 TXD1 Ipd MII Transmit Data Input 19 TXD2 Ipd MII Transmit Data Input 20 TXD3 Ipd MII Transmit Data Input 21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. Pin Number Pin Name Type 1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up resistor. 2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface 3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See details. 4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] PHYAD2 during reset. See 5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] PHYAD3 during reset. See 6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] PHYAD4 during reset. See 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as CRSDV/ pcs_lpbk during reset. See PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. REFCLK 16 TXEN Ipd MII Transmit Enable Input 17 TXD0 Ipd MII Transmit Data Input 18 TXD1 Ipd MII Transmit Data Input 19 TXD2 Ipd MII Transmit Data Input 20 TXD3 Ipd MII Transmit Data Input 21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. Pin Number Pin Name Type 1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up resistor. 2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface 3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See details. 4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] PHYAD2 during reset. See 5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] PHYAD3 during reset. See 6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] PHYAD4 during reset. See 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as CRSDV/ pcs_lpbk during reset. See PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. 16 TXEN Ipd MII Transmit Enable Input 17 TXD0 Ipd MII Transmit Data Input 18 TXD1 Ipd MII Transmit Data Input 19 TXD2 Ipd MII Transmit Data Input 20 TXD3 Ipd MII Transmit Data Input 21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. Pin Function 1 MDIO I/O Management Interface (MII) Data I/O: This pin requires an external 4.7K pull-up resistor. 2 MDC I Management Interface (MII) Clock Input: This pin is synchronous to the MDIO data interface 3 RXD3/ Ipd/O MII Receive Data Output: RXD [3..0], these bits are synchronous with RXCLK. PHYAD1 When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted. The pull-up/pull-down value is latched as PHYADDR [1] during reset. See details. 4 RXD2/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [2] PHYAD2 during reset. See 5 RXD1/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [3] PHYAD3 during reset. See 6 RXD0/ Ipd/O MII Receive Data Output: The pull-up/pull-down value is latched as PHYADDR [4] PHYAD4 during reset. See 7 VDDIO Pwr Digital IO 2.5 /3.3V tolerance power supply. 8 GND GND Ground. 9 RXDV/ Ipd/O MII Receive Data Valid Output: The pull-up/pull-down value is latched as CRSDV/ pcs_lpbk during reset. See PCS_LPBK 10 RXC O MII Receive Clock Output: Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps. 11 RXER/ISO Ipd/O MII Receive Error Output: The pull-up/pull-down value is latched as ISOLATE during reset. See 12 GND GND Ground. 13 VDDC Pwr Digital core 2.5V only power supply. 14 TXER Ipd MII Transmit Error Input. 15 TXC/ Ipu/O MII Transmit Clock Output: RMII Reference Clock Input. 16 TXEN Ipd MII Transmit Enable Input 17 TXD0 Ipd MII Transmit Data Input 18 TXD1 Ipd MII Transmit Data Input 19 TXD2 Ipd MII Transmit Data Input 20 TXD3 Ipd MII Transmit Data Input 21 COL/RMII Ipd/O MII Collision Detect Output: The pull-up/pull-down value is latched as RMII select during reset. See 24 VDDIO Pwr Digital IO 2.5/3.3V tolerance power supply. |
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