April 2005

9

MIC3808/3809

MIC3808/3809

Micrel

Q

S

R

0.2V

VDD

2

OSCILLATOR

OUTPUT

RC

4

Figure 2. Oscillator

The voltage source to the resistor/capacitor timing compo-

oscillator. The oscillator frequency can be roughly approxi-

mated using the following formula:

F_oscillator = 1.41/R*C

Where: frequency is in Hz

Resistance is in Ohms

Capacitance is in Farads.

Graphs of oscillator frequency and dead time vs component

values are shown in the Typical Characteristic section of this

specification. The recommended range of timing resistors

and capacitors is 10kΩ to 200kΩ and 100pF to 1000pF. To

minimize oscillator noise and insure a stable waveform the

following layout rules should be followed:

1. The higher impedance of capacitor values less

than 100pF may causes the oscillator circuit to

become more susceptible to noise. Parasitic pin

and etch trace capacitances become a larger

part of the total RC capacitance and may

influence the desired switching frequency.

2. The circuit board etch between the timing

resistor, capacitor, RC pin and ground must be

kept as short as possible to minimize noise

pickup and insure a stable oscillator waveform.

3. The ground lead of the capacitor must be routed

close to the ground lead of the MIC3808/9.

Current Sensing and Overcurrent Protection

The CS pin features are:

1. Peak current limit

2. Overcurrent limit

3. Internal current sense discharge

4. Front edge blanking

In current mode control, a PWM comparator uses the inductor

current signal and the error amplifier signal to determine the

operating duty cycle. In the MIC3808/9 the signal at the CS

pin is level shifted up before it reaches the PWM comparator

as shown in Figure 1. This allows operation of the error

amplifier and PWM comparator in a linear region.

There are two current limit thresholds in the MIC3808/9; peak

current limit and overcurrent limit. The normal operating

voltage at the CS pin is designed less than these thresholds.

A pulse-by-pulse current limit occurs when the inductor

current signal at the CS pin exceeds the peak current limit

threshold. The on-time is terminated for the remainder of the

switching cycle, regardless of whether OUTA or OUTB is

active.

If the signal at the CS pin goes past the peak threshold and

exceeds the overcurrent limit threshold, the overcurrent limit

comparator forces the soft start node to discharge and

initiates a soft start reset.

An internal FET discharges the CS pin at the end of the

oscillator charge time. The FET turns on when the voltage on

on for the duration of the RC pin discharge time and for

typically 100ns after the start of the next on-time period. The

100ns period at the beginning of the on-time implements a

front edge blanking feature that prevents false triggering of

the PWM comparator due to noise spikes on the leading edge

of the current turn-on signal. The front edge blanking also

sets the minimum on-time for OUTA and OUTB. The timing

diagram for the CS pin is shown in Figure 3.

RC Pin

Max ON time

dead time

Oscillator

Reset

CS Pin

OUTA

OUTB

dead time

Front edge blanking

Minimum ON time

Figure 3. Timing Diagram

Error Amplifier

The error amplifier is part of the voltage control loop of the

power supply. The FB pin is the inverting input to the error

amplifier. The non-inverting input is internally connected to a

reference voltage. The output of the error amplifier, COMP,

is connected to the PWM comparator. A voltage divider

between the error amplifier output (COMP pin) and the PWM

comparator allows the error amplifier to operate in a linear

region for better transient response. The output of the error

amplifier (COMP pin) is limited to typically 3.65V to prevent

the COMP pin from rising up too high during startup or during

a transient condition. This feature improves the transient

response of the power supply.