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K8S6815ETD Datasheet(PDF) 5 Page - Samsung semiconductor |
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K8S6815ETD Datasheet(HTML) 5 Page - Samsung semiconductor |
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5 / 48 page  - 5 - K8S6815ET(B)D datasheet NOR FLASH MEMORY Rev. 1.2 3.0 PIN DESCRIPTION 4.0 PIN CONFIGURATION 44-FBGA : Top View (Ball Down) Pin Name Pin Function A16 - A21 Address Inputs A/DQ0 - A/DQ15 Multiplexed Address/Data input/output CE Chip Enable OE Output Enable RESET Hardware Reset Pin VPP Accelerates Programming WE Write Enable WP Hardware Write Protection Input CLK Clock RDY Ready Output AVD Address Valid Input Vcc Power Supply VSS Ground RDY A21 VSS CLK VCC WE A16 A20 AVD NC VSS A/DQ7 A/DQ6 A/DQ13 A/DQ12 A/DQ3 A/DQ15 A/DQ14 VSS A/DQ5 A/DQ4 A/DQ11 VCC RESET VPP A19 A17 NC WP A18 CE VSS A/DQ2 A/DQ9 A/DQ8 OE A/DQ10 VCC A/DQ1 A/DQ0 123456789 10 A C D B |
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