1Mx36 & 2Mx18 DDRII+ CIO b2 SRAM

K7K3236T2C

K7K3218T2C

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Rev. 1.3 August 2008

The K7K3236T2C and K7K3218T2C are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are orga-

nized as 1,048,576 words by 36bits for K7K3236T2C and 2,097,152 words by 18 bits for K7K3218T2C .

Address, data inputs, and all control signals are synchronized to the input clock ( K or K ). Read data are referenced to echo clock (

CQ or CQ ) outputs. Read address and write address are registered on rising edges of the input K clocks. Common address bus is

used to access address both for read and write operations. The internal burst counter is fixed to 2-bit sequential for both read and

write operations. Synchronous pipeline read and late write enable high speed operations. Simple depth expansion is accomplished

IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoriing package pads attachment status with system.

The K7K3236T2C and K7K3218T2C are implemented with SAMSUNG's high performance 6T CMOS technology and is available in

165pin FBGA packages. Multiple power and ground pins minimize ground bounce.

GENERAL DESCRIPTION

Read Operations

Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K. Address is presented and stored in

the read address register synchronized with K clock. For 2-bit burst DDR operation, it will access two 36-bit or 18-bit data words with

each read command.

The first pipelined data is transfered out of the device triggered by K clock rising edge. Next burst data is triggered by the rising edge

of following K clock rising edge. Continuous read operations are initated with K clock rising edge. And pipelined data are transferred

out of device on every rising edge of both K and K clocks. Initial read data latency is 2 clock cycles when DLL is on.

When the LD is disabled after a read operation, the K7K3236T2C and K7K3218T2C will first complete burst read operation before

entering into deselect mode at the next K clock rising edge. Then output drivers disabled automatically to high impedance state.

Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K. Address is presented and stored in

the write address register synchronized with next K clock. For 2-bit burst DDR operation, it will write two 36-bit or 18-bit data words

with each write command.

The first "late writed" data is transfered and registered in to the device synchronous with next K clock rising edge. Next burst data is

transfered and registered synchronous with following K clock rising edge. Continuous write operations are initated with K rising edge.

And "late writed" data is presented to the device on every rising edge of both K and K clocks. When the LD is disabled, the

K7K3236T2C and K7K3218T2C will enter into deselect mode.

The device disregards input data presented on the same cycle R/W disabled. The K7K3236T2C and K7K3218T2C support byte write

Write Operations