Device Operation

This Sanyo 1 MEG flash memory allows electrical rewrites using a 5 V single-voltage power supply. The LE28C1001M,

T series products are pin and function compatible with the industry standards for this type of product.

Read

The LE28C1001M, T series read operations are controlled by CE and OE. The host must set both pins to the low level to

acquire the output data. CE is used for chip selection. When CE is at the high level, the chip will be in the unselected

state and only draw the standby current. OE is used for output control. The output pins go to the high-impedance state

when either CE or OE is high. See the timing waveforms (Figure 1) for details.

Page Write Operation

The write operation starts when both CE and WE are at the low level, and furthermore OE is at the high level. The write

operation is executed in two stages. The first stage is a byte load cycle in which the host writes to the LE28C1001M, T

series internal page buffers. The second stage is an internal programming cycle in which the data in the page buffer is

written to the nonvolatile memory cell array. In the byte load cycle, the address is latched on the falling edge of either

CE or WE, whichever occurs later. The input data is latched on the rising edge of either CE or WE, whichever occurs

cycle starts, the operation continues until the programming operation is completely done. This operation executes within

5 ms (typical). Figures 2 and 3 show the WE and CE control write cycle timing diagrams, and Figure 10 shows the

flowchart for this operation.

In the page write operation, 128 bytes of data can be written to the LE28C1001M, T series internal page buffer before

the internal programming cycle. All the data in the page buffer is written to the memory cell array during the 5 ms

(typical) internal programming cycle. Therefore the LE28C1001M, T series page write function can rewrite all memory

cells in 5 seconds (typical). The host can perform any other activities desired, such as moving data at other locations

within the system and preparing the data required for the next page write, during the period prior to the completion of the

internal programming cycle. In a given page write operation, all the data bytes loaded into the page buffers must be for

the same page address specified by address lines A7 through A16. All data that was not explicitly loaded into the page

buffer is set to FFH.

Figure 2 shows the page write cycle timing diagram. If the host loads the second data byte into the page buffer within the

thus allowing data to be loaded continuously. The page load cycle terminates if additional data is not loaded into the

from high to low after the last WE rising edge. The data in the page buffer can be rewritten in the next byte load cycle.

The page load period can continue indefinitely as long as the host continues to load data into the device within the 100 µs

byte load cycle. The page that is loaded is determined by the page address of the last byte loaded.

Detecting the Write Operation State

The LE28C1001M, T series products provide two functions for detecting the completion of the write cycle. These

functions are used to optimize the system write cycle time. These functions are based on detecting the states of the Data

polling bit (DQ7) and the toggle bit (DQ6).

Data Polling (DQ7)

The LE28C1001M, T series products output to DQ7 the inverse of the last data loaded during the page and byte load

cycles when the internal programming cycle is in progress. The last data loaded can be read from DQ7 when the internal

programming cycle completes. Figure 4 shows the Data polling cycle timing diagram and Figure 11 shows the flowchart

for this operation.

Toggle Bit (DQ6)

Data values of 0 and 1 are output alternately for DQ6, that is DQ6 is toggled between 0 and 1, during the internal

programming cycle. When the internal programming cycle completes this toggling is stopped and the device becomes

ready to execute the next operation. Figure 5 shows the toggle bit timing diagram and Figure 11 shows the flowchart for

this operation.

No. 5129-4/14

LE28C1001M, T-90/12/15