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K7D163674B Datasheet(PDF) 6 Page - Samsung semiconductor |
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K7D163674B Datasheet(HTML) 6 Page - Samsung semiconductor |
6 / 16 page Rev 1.1 512Kx36 & 1Mx18 SRAM - 6 - Jan. 2005 K7D161874B K7D163674B TRUTH TABLE NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care". - K & K are complementary. K G B1 B2 B3 DQ Operation L XXXX Hi-Z Clock Stop ↑ X H L X Hi-Z No Operation, Pipeline High-Z ↑ L L H H DOUT Load Address, Single Read ↑ L L H L DOUT Load Address, Double Read ↑ X L L H DIN Load Address, Single Write ↑ X L L L DIN Load Address, Double Write ↑ X H H X B Increment Address, Continue 4 Burst Operation for Interleaved Burst (LBO = VDDQ) NOTE : - For Interleave Burst LBO = VDDQ is recommended. If LBO = VDD, it must not exceed 2.63V. Interleaved Burst Case 1 Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Fourth Address 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 BURST SEQUENCE TABLE 4 Burst Operation for Linear Burst (LBO = VSS) Linear Burst Mode Case 1 Case 2 Case 3 Case 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address Fourth Address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0 |
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