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28 page 
SBAS533 – MARCH 2011 Register Address 2Bh (Default = 00h) 7 6 5 4 3 2 1 0 CH B GAIN 0 CH B TEST PATTERNS Bits[7:4] CH B GAIN: Channel B gain programmability These bits set the gain programmability in 0.5dB steps for channel B. 0000 = 0dB gain (default after reset) 0001 = 0.5dB gain 0010 = 1dB gain 0011 = 1.5dB gain 0100 = 2dB gain 0101 = 2.5dB gain 0110 = 3dB gain 0111 = 3.5dB gain 1000 = 4dB gain 1001 = 4.5dB gain 1010 = 5dB gain 1011 = 5.5dB gain 1100 = 6dB gain Bit 3 Always write '0' Bits[2:0] CH B TEST PATTERNS: Channel B data capture These bits verify data capture for channel B. 000 = Normal operation 001 = Outputs all 0s 010 = Outputs all 1s 011 = Outputs toggle pattern. For the ADS424x, output data D[13:0] are an alternating sequence of 10101010101010 and 01010101010101. For the ADS422x, the output data D[11:0] are an alternating sequence of 101010101010 and 010101010101. 100 = Outputs digital ramp. For the ADS424x, output data increment by one LSB (14-bit) every clock cycle from code 0 to code 16383. For the ADS422x, output data increment by one LSB (12-bit) every fourth clock cycle from code 0 to code 4095. 101 = Outputs custom pattern; use registers 3Fh and 40h to set the custom pattern 110 = Unused 111 = Unused 28 Copyright © 2011, Texas Instruments Incorporated |
