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CYF0072V18L-133BGXI Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CYF0072V18L-133BGXI
Description  18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CYF0072V18L-133BGXI Datasheet(HTML) 8 Page - Cypress Semiconductor

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CYF0018V, CYF0036V
CYF0072V
Document Number: 001-53687 Rev. *H
Page 8 of 29
Selecting Word Sizes
The word sizes are configured based on the logic levels on the
PORTSZ pins during the master reset (MRS) cycle only (latched
on low to high edge). The port size cannot be changed during
normal mode of operation and these pins are ignored. Table 1.
explains the pins of D[35:0] and Q[35:0] that will have valid data
in modes where the word size is less than ×36. If word size is
less than ×36, the unused output pins are tri-stated by the device
and unused input pins will be ignored by the internal logic. The
pins with valid data input D[N:0] and output Q[N:0] is given in
Table 1.
Data Valid Signal (DVal)
Data valid (DVal) is an active low signal, synchronized to RCLK
and is provided for easy capture of output data to the user. When
a read operation is performed, the DVal signal goes low along
with output data. This helps user to capture the data without
keeping track of REN to data output latency. This signal also
helps when write and read operations are performed continu-
ously at different frequencies by indicating when valid data is
available at the output port Q[35:0].
Power Up
The device becomes functional after VCC1, VCC2, VCCIO, and
Vref attain minimum stable voltage required as given in Recom-
mended DC Operating Conditions on page 13. The device can
be accessed tPU time after these supplies attain the minimum
required level (see Switching Characteristics on page 15). There
is no particular power sequencing required for the device.
Write Mask and Read Skip Operation
As mentioned in Architecture on page 7, enabling writes but
disabling the inputs (IE HIGH) increments the write pointer
without doing any write operations or altering the contents of the
location.
This feature is called Write Mask and allows user to move the
write pointer without actually writing to the locations. This “write
masking” ability is useful in some video applications such as
Picture In Picture (PIP).
Similarly, during a read operation, if the outputs are disabled by
having the OE high, the read data does not appear on the output
bus; however, the read pointer is incremented.
Programming Flag Offsets and Configuration
Registers
The CYF0072V has ten 8-bit user configurable registers. These
registers contain the almost-full offset (M) and almost-empty (N)
values which decide when the PAF and PAE flags are asserted.
These registers can be programmed into the FIFO in one of two
ways: using either the serial or parallel loading method. The
loading method is selected using the SPI_SEN (Serial Enable)
pin. A low on the SPI_SEN selects the serial method for writing
into the registers. For serial programming, there is a separate
SCLK and a Serial Input (SI). In parallel mode, a low on the load
(LD) pin causes the write and read operation to these registers.
The write and read operation happens from the first location
(0x1) to the last location (0xA) in a sequence. If LD is high, the
writes occur to the FIFO.
In addition to loading register values into the FIFO, it is also
possible to read the current register values. Register values can
be read through the parallel output port regardless of the
programming mode selected (serial or parallel). Register values
cannot be read serially. The registers may be programmed (and
reprogrammed) any time after master reset, regardless of
whether serial or parallel programming is selected.
See Table 3 on page 9 and Table 4 on page 10 for access to
configuration registers in serial and parallel modes.
In parallel mode, the read and write operations loop back when
the maximum address location of the configuration registers is
reached. Simultaneous read and write operations should be
avoided on the configuration registers. Any change in
configuration registers will take effect after eight write clock
cycles(WCLK) cycles.
Table 1. Word Size Selection
PORTSZ[2:0]
Word Size
Active Input Data Pins D[X:0] Active Output Data Pins Q[X:0]
000
×9
D[8:0]
Q[8:0]
001
×12
D[11:0]
Q[11:0]
010
×16
D[15:0]
Q[15:0]
011
×18
D[17:0]
Q[17:0]
100
×20
D[19:0]
Q[19:0]
101
×24
D[23:0]
Q[23:0]
110
×32
D[31:0]
Q[31:0]
111
×36
D[35:0]
Q[35:0]


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