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CY62128EV30LL-45ZAXI Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY62128EV30LL-45ZAXI Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 15 page CY62128EV30 MoBL® Document #: 38-05579 Rev. *I Page 5 of 15 Capacitance Parameter[9] Description Test Conditions Max Unit CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(typ) 10 pF COUT Output capacitance 10 pF Note 9. Tested initially and after any design or process changes that may affect these parameters. 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 12. Full device AC operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) 100 µs. Thermal Resistance Parameter[9] Description Test Conditions TSOP I SOIC STSOP Unit JA Thermal resistance (junction to ambient) Still air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 33.01 48.67 32.56 °C/W JC Thermal resistance (junction to case) 3.42 25.86 3.59 °C/W Figure 4. AC Test Loads and Waveforms VCC VCC OUTPUT R2 30 pF INCLUDING JIG AND SCOPE GND 90% 10% 90% 10% Rise Time = 1 V/ns Fall Time = 1 V/ns OUTPUT V Equivalent to: THEVENIN EQUIVALENT ALL INPUT PULSES RTH R1 Parameters 2.50V 3.0V Unit R1 16667 1103 R2 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min Typ[10] Max Unit VDR VCC for data retention 1.5 – – V ICCDR[11] Data retention current VCC = 1.5 V, CE1 > VCC 0.2 V or CE2 < 0.2 V, VIN > VCC 0.2 V or VIN < 0.2 V Industrial – – 3 µA tCDR[9] Chip deselect to data retention time 0 – – ns tR[12] Operation recovery time 45 – – ns [+] Feedback |
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