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CY8C3445LTI-093 Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CY8C3445LTI-093 Datasheet(HTML) 4 Page - Cypress Semiconductor |
4 / 126 page PSoC® 3: CY8C34 Family Data Sheet Document Number: 001-53304 Rev. *K Page 4 of 126 CY8C34 family these blocks can include four 16-bit timer, counter, and PWM blocks; I2C slave, master, and multi-master; Full-Speed USB; and Full CAN 2.0b. For more details on the peripherals see the “Example Peripherals” section on page 39 of this data sheet. For information on UDBs, DSI, and other digital blocks, see the “Digital Subsystem” section on page 38 of this data sheet. PSoC’s analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.9-percent error over temperature and voltage. The configurable analog subsystem includes: Analog muxes Comparators Voltage references Analog-to-digital converter (ADC) Digital-to-analog converters (DACs) All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The heart of the analog subsystem is a fast, accurate, configurable delta-sigma ADC with these features: Less than 100 µV offset A gain error of 0.2 percent INL less than ±1 LSB DNL less than ±1 LSB SINAD better than 66 dB This converter addresses a wide variety of precision analog applications, including some of the most demanding sensors. Two high-speed voltage or current DACs support 8-bit output signals at update rate of 8 Msps in current DAC (IDAC) and 1 Msps in voltage DAC (VDAC). They can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC and DACs, the analog subsystem provides multiple: Uncommitted opamps Configurable switched capacitor/continuous time (SC/CT) blocks. These support: Transimpedance amplifiers Programmable gain amplifiers Mixers Other similar analog components See the “Analog Subsystem” section on page 50 of this data sheet for more details. PSoC’s 8051 CPU subsystem is built around a single cycle pipelined 8051 8-bit processor running at up to 50 MHz. The CPU subsystem includes a programmable nested vector interrupt controller, DMA controller, and RAM. PSoC’s nested vector interrupt controller provides low latency by allowing the CPU to vector directly to the first address of the interrupt service routine, bypassing the jump instruction required by other architectures. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The processor speed itself is configurable, allowing you to tune active power consumption for specific applications. PSoC’s nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 64 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling bootloaders. You can enable an error correcting code (ECC) for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Up to 2 KB of byte-writeable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after power-on reset (POR). The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive[4], CapSense[5], flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All of the features of the PSoC I/Os are covered in detail in the “I/O System and Routing” section on page 32 of this data sheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The Internal Main Oscillator (IMO) is the master clock base for the system, and has 1-percent accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 24 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. Notes 4. This feature on select devices only. See Ordering Information on page 113 for details. 5. GPIOs with opamp outputs are not recommended for use with CapSense. [+] Feedback |
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