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K4B4G0446B-MCH9 Datasheet(PDF) 4 Page - Samsung semiconductor |
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K4B4G0446B-MCH9 Datasheet(HTML) 4 Page - Samsung semiconductor |
4 / 59 page Page 4 of 59 Rev. 1.0 March 2009 DDP 4Gb DDR3 SDRAM K4B4G0446B K4B4G0846B 9.9 ODT Timing Definitions .............................................................................................................. 25 9.9.1 Test Load for ODT Timings ................................................................................................. 25 9.9.2 ODT Timing Definition ........................................................................................................ 25 10.0 IDD Specification Parameters and Test Conditions ............................................................. 28 10.1 IDD Measurement Conditions .................................................................................................... 28 10.2 IDD Specifications definition ..................................................................................................... 30 11.0 DDP 4Gb DDR3 SDRAM B-die IDD Spec Table ..................................................................... 37 12.0 Input/Output Capacitance ....................................................................................................... 38 13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600 .............................. 39 13.1 Clock specification ............................................................................................................. 39 13.1.1 Definition for tCK (avg) ..................................................................................................... 39 13.1.2 Definition for tCK (abs) ..................................................................................................... 39 13.1.3 Definition for tCH(avg) and tCL(avg) ................................................................................... 39 13.1.4 Definition for note for tJIT(per), tJIT(per,Ick) ........................................................................ 39 13.1.5 Definition for tJIT(cc), tJIT(cc,Ick) ...................................................................................... 39 13.1.6 Definition for tERR(nper) ................................................................................................... 39 13.2 Refresh Parameters by Device Density ....................................................................................... 40 13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ............................................. 40 13.3.1 Speed Bin Table Notes........................................................................................................................... 43 14.0 Timing Parameters by Speed Grade ...................................................................................... 44 14.1 Jitter Notes ............................................................................................................................. 47 14.2 Timing Parameter Notes ........................................................................................................... 48 14.3 Address / Command Setup, Hold and Derating: ........................................................................... 49 14.4 Data Setup, Hold and Slew Rate Derating: .................................................................................. 55 |
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