CY7C1266KV18 datasheet(8/28 Pages) CYPRESS

Part #	CY7C1266KV18

Description	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)

Download	28 Pages

Scroll/Zoom	100%

Manufacturer	CYPRESS [Cypress Semiconductor]

Direct Link	http://www.cypress.com

Logo

8 / 28 page

CY7C1266KV18, CY7C1277KV18

CY7C1268KV18, CY7C1270KV18

Document Number: 001-57835 Rev. *C

Page 8 of 28

DOFF

Input

PLL turn off

 active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull-up through a 10 K

 or less pull-up resistor. The device behaves in DDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz

with DDR I timing.

TDO

Output

TDO for JTAG

TCK

Input

TCK pin for JTAG

TDI

Input

TDI pin for JTAG

TMS

Input

TMS pin for JTAG

NC

N/A

Not connected to the die. Can be tied to any voltage level.

NC/72M

Input

Not connected to the die. Can be tied to any voltage level.

NC/144M

Input

Not connected to the die. Can be tied to any voltage level.

NC/288M

Input

Not connected to the die. Can be tied to any voltage level.

VREF

Input-

reference

Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC

measurement points.

VDD

Power supply Power supply inputs to the core of the device

VSS

Ground

Ground for the device

VDDQ

Power supply Power supply inputs for the outputs of the device

Pin Definitions (continued)

Pin Name

I/O

Pin Description

[+] Feedback

Similar Part No. - CY7C1266KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C12661KV18	903Kb / 30P	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1266V18	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1266V18-300BZC	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1266V18-300BZI	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1266V18-300BZXC	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

More results

Similar Description - CY7C1266KV18

Manufacturer	Part #	Datasheet	Description
Cypress Semiconductor	CY7C1246V18	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Renesas Technology Corp	RMQCHA3636DGBA	846Kb / 30P	36-Mbit DDR??II SRAM 2-word Burst Architecture (2.0 Cycle Read latency)
Cypress Semiconductor	CY7C1246KV18	913Kb / 28P	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Cypress Semiconductor	CY7C12461KV18	895Kb / 29P	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Renesas Technology Corp	RMQCLA3636DGBA	885Kb / 30P	36-Mbit DDR™ II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) Dec. 01, 2014
	RMQCHA3636DGBA	846Kb / 30P	36-Mbit DDR™ II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) Dec. 01, 2014
	RMQCBA3636DGBA	849Kb / 30P	36-Mbit DDR??II SRAM 2-word Burst Architecture (2.5 Cycle Read latency)
Cypress Semiconductor	CY7C1266V18	1Mb / 27P	36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
	CY7C1546KV18	959Kb / 31P	72-Mbit DDR II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
	CY7C12661KV18	903Kb / 30P	36-Mbit DDR II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)

More results

CY7C1266KV18 Datasheet(PDF) 8 Page - Cypress Semiconductor

CY7C1266KV18 Datasheet(HTML) 8 Page - Cypress Semiconductor

Similar Part No. - CY7C1266KV18

Similar Description - CY7C1266KV18

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL