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CY2XL11 Datasheet(PDF) 2 Page - Cypress Semiconductor |
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CY2XL11 Datasheet(HTML) 2 Page - Cypress Semiconductor |
2 / 9 page CY2XL11 Document Number: 001-42886 Rev. *F Page 2 of 9 Frequency Table Input Crystal Frequency (MHz) PLL Multiplier Value Output Frequency (MHz) 25 4 100 Absolute Maximum Conditions Parameter Description Condition Min Max Unit VDD Supply voltage – –0.5 4.4 V VIN [1] Input voltage, DC Relative to VSS –0.5 VDD + 0.5 V TS Temperature, storage Non operating –65 150 °C TJ Temperature, junction – – 135 °C ESDHBM ESD protection (human body model) JEDEC STD 22-A114-B 2000 – V UL–94 Flammability rating At 1/8 inch V–0 Θ JA [2] Thermal resistance, junction to ambient 0 m/s airflow 100 °C/W 1 m/s airflow 91 2.5 m/s airflow 87 Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. Outputs are terminated with 100 Ω between CLK and CLK#. Refer to Figure 8 on page 5. 4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistor. 5. Not 100% tested, guaranteed by design and characterization. 6. Refer to Figure 2 on page 4. 7. Refer to Figure 3 on page 4. Operating Conditions Parameter Description Min Max Unit VDD 3.3 V supply voltage 3.135 3.465 V 2.5 V supply voltage 2.375 2.625 V TA Ambient temperature –5 70 °C TPU Power up time for all VDD to reach minimum specified voltage (ensure power ramps is monotonic) 0.05 500 ms DC Electrical Characteristics Parameter Description Test Conditions Min Typ Max Unit IDD [4] Power supply current with output terminated VDD = 3.465 V, OE = VDD, output terminated – – 120 mA VDD = 2.625 V, OE = VDD, output terminated – – 115 mA VOD [6] LVDS differential output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# 247 – 454 mV ΔV OD [6] Change in VOD between comple- mentary output states VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# –– 50 mV VOS [7] LVDS offset output voltage VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# 1.125 – 1.375 V ΔV OS Change in VOS between comple- mentary output states VDD = 3.3 V or 2.5 V, RTERM = 100 Ω between CLK and CLK# –– 50 mV IOZ Output leakage current Three-state output, unterminated, measured on one pin while floating the other pin, OE = VSS –35 – 35 μA [+] Feedback |
Similar Part No. - CY2XL11_11 |
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Similar Description - CY2XL11_11 |
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