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SST25VF032B Datasheet(PDF) 8 Page - Microchip Technology |
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SST25VF032B Datasheet(HTML) 8 Page - Microchip Technology |
8 / 31 page ©2011 Silicon Storage Technology, Inc. S71327-04-000 02/11 8 32 Mbit SPI Serial Flash SST25VF032B Data Sheet A Microchip Technology Company Auto Address Increment (AAI) The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming mode or Byte-Program mode. The default at power up is Byte-Program mode. Block Protection (BP3,BP2, BP1, BP0) The Block-Protection (BP3, BP2, BP1, BP0) bits define the size of the memory area, as shown in Table 4, to be software protected against any memory Write (Program or Erase) operation. The Write-Status- Register (WRSR) instruction is used to program the BP3, BP2, BP1 and BP0 bits as long as WP# is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After power-up, BP3, BP2, BP1 and BP0 are set to the defaults specified in Table 4. Block Protection Lock-Down (BPL) WP# pin driven low (VIL), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP3, BP2, BP1, and BP0 bits. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is “Don’t Care”. After power-up, the BPL bit is reset to 0. Table 4: Software Status Register Block Protection FOR SST25VF032B1 1. X = Don’t Care (RESERVED) default is “0 Protection Level Status Register Bit2 2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected) Protected Memory Address BP3 BP2 BP1 BP0 32 Mbit None X 0 0 0 None Upper 1/64 X 0 0 1 3F0000H-3FFFFFH Upper 1/32 X 0 1 0 3E0000H-3FFFFFH Upper 1/16 X 0 1 1 3C0000H-3FFFFFH Upper 1/8 X 1 0 0 380000H-3FFFFFH Upper 1/4 X 1 0 1 300000H-3FFFFFH Upper 1/2 X 1 1 0 200000H-3FFFFFH All Blocks X 1 1 1 000000H-3FFFFFH T4.0 1327 |
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