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TPS799xx Datasheet(PDF) 5 Page - Texas Instruments |
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TPS799xx Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 158 page  SM320F28335-HT www.ti.com SPRS682 – DECEMBER 2010 List of Figures 2-1 181-Pin GB ........................................................................................................................ 13 3-1 Functional Block Diagram ...................................................................................................... 26 3-2 Memory Map ...................................................................................................................... 28 3-3 External and PIE Interrupt Sources ............................................................................................ 41 3-4 External Interrupts ................................................................................................................ 41 3-5 Multiplexing of Interrupts Using the PIE Block ............................................................................... 42 3-6 Clock and Reset Domains ...................................................................................................... 45 3-7 OSC and PLL Block Diagram ................................................................................................... 46 3-8 Using a 3.3-V External Oscillator ............................................................................................... 47 3-9 Using a 1.9-V External Oscillator ............................................................................................... 47 3-10 Using the Internal Oscillator .................................................................................................... 47 3-11 Watchdog Module ................................................................................................................ 49 4-1 DMA Functional Block Diagram ................................................................................................ 52 4-2 CPU-Timers ....................................................................................................................... 53 4-3 CPU-Timer Interrupt Signals and Output Signal ............................................................................. 53 4-4 Multiple PWM Modules .......................................................................................................... 55 4-5 ePWM Submodules Showing Critical Internal Signal Interconnections ................................................... 58 4-6 eCAP Functional Block Diagram ............................................................................................... 61 4-7 eQEP Functional Block Diagram ............................................................................................... 62 4-8 Block Diagram of the ADC Module ............................................................................................ 65 4-9 ADC Pin Connections With Internal Reference .............................................................................. 66 4-10 ADC Pin Connections With External Reference ............................................................................. 67 4-11 McBSP Module .................................................................................................................. 70 4-12 eCAN Block Diagram and Interface Circuit ................................................................................... 73 4-13 eCAN-A Memory Map ........................................................................................................... 74 4-14 eCAN-B Memory Map ........................................................................................................... 75 4-15 Serial Communications Interface (SCI) Module Block Diagram ............................................................ 79 4-16 SPI Module Block Diagram (Slave Mode) .................................................................................... 82 4-17 I2C Peripheral Module Interfaces .............................................................................................. 83 4-18 GPIO MUX Block Diagram ...................................................................................................... 85 4-19 Qualification Using Sampling Window ......................................................................................... 90 4-20 External Interface Block Diagram .............................................................................................. 91 4-21 Typical 16-bit Data Bus XINTF Connections ................................................................................. 92 4-22 Typical 32-bit Data Bus XINTF Connections ................................................................................. 92 6-1 SM320F28335 Operating Life Derating Chart ................................................................................ 94 6-2 Typical Operational Current Versus Frequency for TA = 25°C ........................................................... 100 6-3 Typical Operational Current Versus Frequency for TA = 210°C .......................................................... 100 6-4 Emulator Connection Without Signal Buffering for the DSP .............................................................. 101 6-5 3.3-V Test Load Circuit ......................................................................................................... 102 6-6 Clock Timing ..................................................................................................................... 105 6-7 Power-on Reset ................................................................................................................. 106 6-8 Warm Reset ..................................................................................................................... 107 6-9 Example of Effect of Writing Into PLLCR Register ......................................................................... 108 6-10 General-Purpose Output Timing .............................................................................................. 109 6-11 Sampling Mode ................................................................................................................. 109 6-12 General-Purpose Input Timing ................................................................................................ 110 6-13 IDLE Entry and Exit Timing .................................................................................................... 111 Copyright © 2010, Texas Instruments Incorporated List of Figures 5 |
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