ZL9101M

9

FN7669.1

January 26, 2011

Functional Description

Output Voltage Selection

The output voltage may be set to a voltage between 0.6V and

4.0V provided that the input voltage is higher than the desired

output voltage by an amount sufficient to prevent the device

from exceeding its maximum duty cycle specification.

The VSET pin is used to set the output voltage to levels as shown

SGND.

The output voltage may also be set to any value between 0.6V and 4.0V

Application Note AN2033 for details.

Soft-start Delay and Ramp Times

It may be necessary to set a delay from when an enable signal is

received until the output voltage starts to ramp to its target

value. In addition, the designer may wish to precisely set the time

period has expired. These features may be used as part of an

overall inrush current management strategy or to precisely

control how fast a load IC is turned on. The ZL9101M gives the

system designer several options for precisely and independently

controlling both the delay and ramp time periods.

The soft-start delay period begins when the EN pin is asserted

and ends when the delay time expires.

The soft-start delay and ramp times are set to custom values via the

begin its ramp-up after the internal circuitry has initialized

(approximately 2ms). When the soft-start ramp period is set to 0ms, the

output will ramp up as quickly as the output load capacitance and loop

settings will allow. It is generally recommended to set the soft-start

ramp to a value greater than 500µs to prevent inadvertent fault

conditions due to excessive inrush current.

Power Good

The ZL9101M provides a Power Good (PG) signal that indicates

the output voltage is within a specified tolerance of its target

level and no fault condition exists. By default, the PG pin will

assert if the output is within 10% of the target voltage. These

limits and the polarity of the pin may be changed via the

A PG delay period is defined as the time from when all conditions

within the ZL9101M for asserting PG are met to when the PG pin

is actually asserted. This feature is commonly used instead of

using an external reset controller to control external digital logic.

By default, the ZL9101M PG delay is set equal to the soft-start

ramp time setting. Therefore, if the soft-start ramp time is set to

10ms, the PG delay will be set to 10ms. The PG delay may be set

described in Application Note AN2033.

Switching Frequency and PLL

The ZL9101M incorporates an internal phase-locked loop (PLL) to

clock the internal circuitry. The PLL can be driven by an external

clock source connected to the SYNC pin. When using the internal

oscillator, the SYNC pin can be configured as a clock source.

The internal switching frequency of the ZL9101M is 615kHz.

Loop Compensation

The ZL9101M operates as a voltage-mode synchronous buck

controller with a fixed frequency PWM scheme. The module is

refer to Application Note AN2033 for further details.

TABLE 1. OUTPUT VOLTAGE RESISTOR SETTINGS

(V)

(kΩ)

0.60

10

0.65

11

0.70

12.1

0.75

13.3

0.80

14.7

0.85

16.2

0.90

17.8

0.95

19.6

1.00

21.5

1.05

23.7

1.10

26.1

1.15

28.7

1.20

31.6

1.25

34.8

1.30

38.3

1.40

42.2

1.50

46.4

1.60

51.1

1.70

56.2

1.80

61.9

1.90

68.1

2.00

75

2.10

82.5

2.20

90.9

2.30

100

2.50

110

2.80

121

3.00

133

3.30

147

4.00

162