LC74950BG

No.A1647-11/37

Timing Chart

Note: For the initial setting of the registers

Details of the functions

1. Selection of input pins

Registers related to the selection of input pins

Name

Functions

Sub address

bit width

AINSEL

Video input select control

Analog video input select

0: YGIN0/CBIN0/CRIN0

1: YGIN1/CBIN1/CRIN1

0x22

1

• Video input selector function

The video input signal used for actual processing can be selected out of the two systems of video input.

AINSEL=0: YGIN0/CBIN0/CRIN0

AINSEL=1: YGIN1/CBIN1/CRIN1

2. Input format

Registers related to the selection of the input format

Name

Functions

Sub address

bit width

SELYCRGB

This register switches between the YCbCr input and RGB input.

0: YCbCr, 1: RGB

0x14

1

SYNCON

For YCbCr input, this register, by cutting off the digitally clamped sync component of the

Y video signal, sets the applicable gain adjustment function to ON or OFF.

This must be set to 0 for the RGB input (SELYCRGB=1).

0: ON, 1: OFF

0x1B

1

All the inputs listed below can be connected to the analog ports. It is also possible to switch between the inputs of two

systems and use the one selected.

YCbCr/YPbPr input (480I/576I, 480P/576P): Component input

RGB: RGB input

3. Operating modes

Register related to the selection of operating mode

Name

Functions

Sub address

bit width

CLKSEL

Operating mode selection

000: External clock mode (PLL not used)

001: External clock mode (PLL used)

010: H lock PLL mode

011: Panel PLL mode <1>

100: Panel PLL mode <2>

0x00

3

N

CLKIN

Output data

Analog input

N+1

N+2

N-50

N-49

N

N+1