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HT1622 Datasheet(PDF) 7 Page - Holtek Semiconductor Inc |
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HT1622 Datasheet(HTML) 7 Page - Holtek Semiconductor Inc |
7 / 15 page A.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS1 System Clock 5V On-chip RC oscillator 24 32 40 kHz fSYS2 System Clock ¾ External clock source ¾ 32 ¾ kHz fLCD1 LCD Frame Frequency 5V On-chip RC oscillator 48 64 80 Hz fLCD2 LCD Frame Frequency ¾ External clock source ¾ 64 ¾ Hz tCOM LCD Common Period ¾ n: Number of COM ¾ n/fLCD ¾ sec fCLK1 Serial Data Clock (WR Pin) 3V Duty cycle 50% 4 ¾ 150 kHz 5V 4 ¾ 300 kHz fCLK2 Serial Data Clock (RD Pin) 3V Duty cycle 50% ¾¾ 75 kHz 5V ¾¾ 150 kHz tCS Serial Interface Reset Pulse Width (Figure 3) ¾ CS 500 600 ¾ ns tCLK WR,RD Input Pulse Width (Figure 1) 3V Write mode 3.34 ¾ 125 ms Read mode 6.67 ¾¾ 5V Write mode 1.67 ¾ 125 ms Read mode 3.34 ¾¾ tr,tf Rise or Fall Time Serial Data Clock Width (Figure 1) ¾¾ ¾ 120 160 ns tsu Setup Time for DATA to WR,RD Clock Width (Figure 2) ¾¾ 60 120 ¾ ns tsu1 Setup Time for CS to WR,RD Clock Width (Figure 3) ¾¾ 500 600 ¾ ns th Hold Time for DATA to WR,RD Clock Width (Figure 2) ¾¾ 500 600 ¾ ns th1 Hold Time for CS to WR,RD Clock Width (Figure 3) ¾¾ 50 100 ¾ ns fTONE Tone Frequency (2kHz) 5V On-chip RC oscillator 1.5 2.0 2.5 kHz Tone Frequency (4kHz) 3.0 4.0 5.0 kHz tOFF VDD OFF Times (Figure 4) ¾ VDD drop down to 0V 20 ¾¾ ms tSR VDD Rising Slew Rate (Figure 4) ¾¾ 0.05 ¾¾ V/ms tRSTD Delay Time after Reset (Figure 4) ¾¾ 1 ¾¾ ms Note: 1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal Power-on Reset (POR) circuit will not operate normally. 2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for 20ms (min.) before rising to the normal operating voltage. HT1626 Rev. 1.60 7 November 9, 2010 PATENTED |
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