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INTC1Register - Alldevices Bit 7 6 5 4 3 2 1 0 Name ¾ ¾ TBF ADF ¾ ¾ TBE ADE R/W ¾ ¾ R/W R/W ¾ ¾ R/W R/W POR ¾ ¾ 0 0 ¾ ¾ 0 0 Bit7~6 unimplemented,readas ²0² Bit5 TBF:TimeBaseeventinterruptrequestflag 0:inactive 1:active Bit4 ADF:A/DConversioninterruptrequestflag 0:inactive 1:active Bit3~2 unimplemented,readas ²0² Bit1 TBE:Timebaseeventinterruptenable 0:disable 1:enable Bit0 ADE:A/DConversioninterruptenable 0:disable 1:enable Timer/EventCounterInterrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. TimeBaseInterrupt For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. ProgrammingConsiderations By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Sleep Mode. HT46R064D/065D/066D EnhancedA/DType8-Bit OTP MCU withLEDDriver Rev.1.00 69 January12,2011 |
