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CYONS2000 Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CYONS2000 Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 36 page CYONS2000 Document Number: 001-44044 Rev. *G Page 5 of 36 Pin Description This section describes, lists, and illustrates the CYONS2000 device pins and pinout configurations. The CYONS2000 is available in a 42-pin quad flat no-leads (QFN) package. Table 1. CYONS2000 Pin Description Pin Name Digital Analog Description 1 XRES I Active high external reset with internal pull-down 2 DVSS Power Power Digital ground 3 DNU Do not use 4 DVSS Power Power Digital ground 5 DVDD Power Power Digital supply voltage and regulated output (see Power Supply Connections on page 11) 6 VREGD Power Power Digital VREG 7 AVDD Power Power Analog supply voltage 8 VREGA Power Power Analog VREG 9 P2[7] I/O I GPIO port 2 pin 7 10 P1[5] IOHR I SPI MISO, I2C_SDA, GPIO port 1 pin 5 11 P1[3] IOHR I SPI CLK, GPIO port 1 pin 3 12 P2[3] I/O I GPIO port 2 pin 3 13 P2[5] I/O I GPIO port 2 pin 5 14 P1[7] IOHR I SPI SS, I2C_SCL, GPIO port 1 pin 7 15 P1[1] IOHR I SPI MOSI, ISSP CLK[1], I2C_SCL, GPIO port 1 pin 1 16 P3[3] IOHR I HCLK (OCD high speed clock output), GPIO port 3 pin 3 17 P1[0] I/O I ISSP DATA[1], I2C_SDA, GPIO port 1 pin 0 18 P3[5] I/O I CCLK (OCD CPU clock output), GPIO port 3 pin 5 19 P1[6] IOHR I GPIO port 1 pin 6 20 P1[2] IOHR I GPIO port 1 pin 2 21 P2[2] I/O I GPIO port 2 pin 2 22 P3[7] I/O I OCDOE (OCD mode direction pin), GPIO port 3 pin 7 23 P3[1] I/O I OCDO (OCD odd data output), GPIO port 3 pin 1 24 OCDE OCD OCD OCDE (OCD even data output) 25 AVSS Power Power Analog ground 26 P2[1] I/O I GPIO port 2 pin 1 27 P2[0] I/O I GPIO port 2 pin 0 28 P1[4] IOHR I EXT CLK, GPIO port 1 pin 4 29 P2[4] I/O I GPIO port 2 pin 4 30 DVSS Power Power Digital ground 31 P2[6] I/O I GPIO port 2 pin 6 32 P0[0] I/O I GPIO port 0 pin 0 33 P0[2] I/O I GPIO port 0 pin 2 34 P0[4] I/O I GPIO port 0 pin 4 35 P0[6] I/O I GPIO port 0 pin 6 36 P0[1] I/O I GPIO port 0 pin 1 [+] Feedback |
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