32-Mbit (2 M × 16 / 4 M × 8) Static RAM

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-09880 Rev. *G

Revised February 22, 2011

32-Mbit (2 M × 16 / 4 M × 8) Static RAM

Features

or as 4 M x 8 static RAM (SRAM)

optimum speed and power

Functional Description

The CY62177EV30 is a high performance CMOS static RAM

organized as 2 M words by 16 bits and 4 M words by 8 bits[1].

This device features advanced circuit design to provide ultra low

active current. It is ideal for providing More Battery Life



The device also has an automatic power down feature that

significantly reduces power consumption by 99 percent when

addresses are not toggling. The device can also be put into

Byte High Enable and Byte Low Enable are disabled (BHE, BLE

LOW).

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte

Low Enable (BLE) is LOW, then data from the memory location

description of read and write modes.

Pin #13 of the 48 TSOP I package is an DNU pin that must be

left floating at all times to ensure proper application

.

DATA IN DRIVERS

OE

WE

BLE

BHE

Power-Down

Circuit

BHE

BLE

BYTE

COLUMN DECODER

2M × 16

RAM Array

Logic Block Diagram

Note

1. For best practice recommendations, refer to the Cypress application note System Design Guidelines.

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