Document Number : 38-05328 Rev. *I

Page 6 of 17

Data Retention Waveform[14]

Parameter[15]

Description

55 ns

70 ns

Unit

Min

Max

Min

Max

Read Cycle

Read cycle time

55

–

70

–

ns

Address to data valid

–

55

–

70

ns

Data hold from address change

10

–

10

–

ns

–

55

–

70

ns

OE LOW to data valid

–

25

–

35

ns

OE LOW to LOW Z[16]

5–

5

–

ns

OE HIGH to High Z[16, 17]

–20

–

25

ns

[16]

10

–

10

–

ns

[16, 17]

–20

–

25

ns

0

–

0

–

ns

–

55

–

70

ns

BLE/BHE LOW to data valid

–

55

–

70

ns

BLE/BHE LOW to Low Z[16]

10

–

10

–

ns

BLE/BHE HIGH to HIGH Z[16, 17]

–20

–

25

ns

Write Cycle[18]

Write cycle time

55

–

70

–

ns

40

–

60

–

ns

Address set-up to write end

40

–

60

–

ns

Address hold from write end

0

–

0

–

ns

Address set-up to write start

0

–

0

–

ns

WE pulse width

40

–

45

–

ns

BLE/BHE LOW to write end

40

–

60

–

ns

Data set-up to write end

25

–

30

–

ns

Data hold from write end

0

–

0

–

ns

WE LOW to High-Z[16, 17]

–20

–

25

ns

WE HIGH to Low-Z[16]

10

–

10

–

ns

Notes

14. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.

device.

and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates

the Write.

DATA RETENTION MODE

BHE

or