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CY62138FV30LL-45ZSXI Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY62138FV30LL-45ZSXI
Description  2-Mbit (256K x 8) Static RAM
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY62138FV30LL-45ZSXI Datasheet(HTML) 4 Page - Cypress Semiconductor

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CY62138FV30 MoBL®
Document #: 001-08029 Rev. *I
Page 4 of 16
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature................................. –65 °C to +150 °C
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Supply voltage to ground
potential ..........................................................–0.3 V to 3.9 V
DC voltage applied to outputs
in High-Z State [4, 5] ........................................–0.3 V to 3.9 V
DC input voltage [4, 5]......................................–0.3 V to 3.9 V
Output current into outputs (LOW) .............................. 20 mA
Static Discharge Voltage......................................... > 2001 V
(MIL-STD-883, Method 3015)
Latch-up current ..................................................... > 200 mA
Product
Range
Ambient
Temperature
VCC [6]
CY62138FV30LL Ind’l/Auto-A –40 °C to +85 °C 2.2 V to 3.6 V
Electrical Characteristics (Over the Operating Range)
Parameter
Description
Test Conditions
45 ns (Ind’l/Auto-A)
Unit
Min
Typ [7]
Max
VOH
Output HIGH voltage
IOH = –0.1 mA
2.0
V
IOH = –1.0 mA, VCC > 2.70 V
2.4
V
VOL
Output LOW voltage
IOL = 0.1 mA
0.4
V
IOL = 2.1 mA, VCC > 2.70 V
0.4
V
VIH
Input HIGH voltage
VCC = 2.2 V to 2.7 V
1.8
VCC + 0.3V
V
VCC= 2.7 V to 3.6 V
2.2
VCC + 0.3V
V
VIL
Input LOW voltage
VCC = 2.2 V to 2.7 V For BGA package
–0.3
0.6
V
VCC= 2.7 V to 3.6 V
–0.3
0.8
V
VCC = 2.2 V to 3.6 V For other packages
–0.3
0.6
V
IIX
Input leakage current
GND < VI < VCC
–1
+1
A
IOZ
Output leakage current
GND < VO < VCC,
output disabled
–1
+1
A
ICC
VCC Operating supply current
f = fmax = 1/tRC
VCC = VCCmax
IOUT = 0 mA
CMOS levels
–13
18
mA
f = 1 MHz
1.6
2.5
ISB1[8]
Automatic CE Power-down
Current CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V, VIN < 0.2 V),
f = fmax (address and data only),
f = 0 (OE, and WE), VCC = 3.60 V
–1
5
A
ISB2 [8]
Automatic CE Power-down
Current CMOS inputs
CE1 > VCC – 0.2 V or CE2 < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = 3.60 V
–1
5
A
Capacitance
Parameter[9]
Description
Test Conditions
Max
Unit
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
VCC = VCC(typ.)
10
pF
COUT
Output Capacitance
10
pF
Notes
4. VIL(min) = 2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC+0.75V for pulse durations less than 20 ns.
6. Full device AC operation assumes a 100
s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C
8. Chip enables (CE1 and CE2) must be at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
9. Tested initially and after any design or process changes that may affect these parameters.
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