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CY62137FV18LL-55BVXI Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY62137FV18LL-55BVXI Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 16 page CY62137FV18 MoBL® Document #: 001-08030 Rev. *H Page 7 of 16 Switching Characteristics Over the Operating Range Parameter[16, 17] Description 55 ns Unit Min Max Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid –55 ns tDOE OE LOW to data valid –25 ns tLZOE OE LOW to low Z [18] 5– ns tHZOE OE HIGH to high Z [18, 19] –18 ns tLZCE CE LOW to low Z [18] 10 – ns tHZCE CE HIGH to high Z [18, 19] –18 ns tPU CE LOW to power up 0– ns tPD CE HIGH to power down –55 ns tDBE BLE/BHE LOW to data valid –55 ns tLZBE BLE/BHE LOW to Low Z [18] 10 – ns tHZBE BLE/BHE HIGH to High Z [18, 19] –18 ns Write Cycle [20] tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tBW BLE/BHE LOW to write end 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to high Z [18, 19] –18 ns tLZWE WE HIGH to low Z [18] 10 – ns Notes 16. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 5. 17. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 18. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 19. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state 20. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. [+] Feedback |
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